From: Greg Kroah-Hartman Date: Mon, 19 Jan 2015 13:27:57 +0000 (+0800) Subject: 3.14-stable patches X-Git-Tag: v3.10.66~53 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=08513ad76db9ce9b269c7d5bf081dab7d7e0ad08;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: arc-move-peripherals-to-match-model-to-fpga.patch arc-switch-to-generic-entry-end-assembler-annotations.patch drm-i915-force-the-cs-stall-for-invalidate-flushes.patch drm-i915-invalidate-media-caches-on-gen7.patch drm-nv4c-mc-disable-msi.patch --- diff --git a/queue-3.14/arc-move-peripherals-to-match-model-to-fpga.patch b/queue-3.14/arc-move-peripherals-to-match-model-to-fpga.patch new file mode 100644 index 00000000000..cf2b41464c3 --- /dev/null +++ b/queue-3.14/arc-move-peripherals-to-match-model-to-fpga.patch @@ -0,0 +1,69 @@ +From e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b Mon Sep 17 00:00:00 2001 +From: Vineet Gupta +Date: Wed, 1 Oct 2014 14:28:36 +0530 +Subject: ARC: [nsimosci] move peripherals to match model to FPGA + +From: Vineet Gupta + +commit e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b upstream. + +This allows the sdplite/Zebu images to run on OSCI simulation platform + +Signed-off-by: Vineet Gupta +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arc/boot/dts/nsimosci.dts | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/arch/arc/boot/dts/nsimosci.dts ++++ b/arch/arc/boot/dts/nsimosci.dts +@@ -20,7 +20,7 @@ + /* this is for console on PGU */ + /* bootargs = "console=tty0 consoleblank=0"; */ + /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; ++ bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; + }; + + aliases { +@@ -46,9 +46,9 @@ + #interrupt-cells = <1>; + }; + +- uart0: serial@c0000000 { ++ uart0: serial@f0000000 { + compatible = "ns8250"; +- reg = <0xc0000000 0x2000>; ++ reg = <0xf0000000 0x2000>; + interrupts = <11>; + clock-frequency = <3686400>; + baud = <115200>; +@@ -57,21 +57,21 @@ + no-loopback-test = <1>; + }; + +- pgu0: pgu@c9000000 { ++ pgu0: pgu@f9000000 { + compatible = "snps,arcpgufb"; +- reg = <0xc9000000 0x400>; ++ reg = <0xf9000000 0x400>; + }; + +- ps2: ps2@c9001000 { ++ ps2: ps2@f9001000 { + compatible = "snps,arc_ps2"; +- reg = <0xc9000400 0x14>; ++ reg = <0xf9000400 0x14>; + interrupts = <13>; + interrupt-names = "arc_ps2_irq"; + }; + +- eth0: ethernet@c0003000 { ++ eth0: ethernet@f0003000 { + compatible = "snps,oscilan"; +- reg = <0xc0003000 0x44>; ++ reg = <0xf0003000 0x44>; + interrupts = <7>, <8>; + interrupt-names = "rx", "tx"; + }; diff --git a/queue-3.14/arc-switch-to-generic-entry-end-assembler-annotations.patch b/queue-3.14/arc-switch-to-generic-entry-end-assembler-annotations.patch new file mode 100644 index 00000000000..e2bb39664e1 --- /dev/null +++ b/queue-3.14/arc-switch-to-generic-entry-end-assembler-annotations.patch @@ -0,0 +1,463 @@ +From ec7ac6afd07b2d958aab9dfc0a686300b856922a Mon Sep 17 00:00:00 2001 +From: Vineet Gupta +Date: Fri, 7 Feb 2014 13:47:43 +0530 +Subject: ARC: switch to generic ENTRY/END assembler annotations + +From: Vineet Gupta + +commit ec7ac6afd07b2d958aab9dfc0a686300b856922a upstream. + +With commit 9df62f054406 "arch: use ASM_NL instead of ';'" the generic +macros can handle the arch specific newline quirk. Hence we can get rid +of ARC asm macros and use the "C" style macros. + +Signed-off-by: Vineet Gupta +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arc/include/asm/linkage.h | 14 ----------- + arch/arc/kernel/ctx_sw_asm.S | 2 - + arch/arc/kernel/entry.S | 52 ++++++++++++++++++++--------------------- + arch/arc/lib/memcmp.S | 6 ++-- + arch/arc/lib/memcpy-700.S | 6 ++-- + arch/arc/lib/memset.S | 10 +++---- + arch/arc/lib/strchr-700.S | 6 ++-- + arch/arc/lib/strcmp.S | 6 ++-- + arch/arc/lib/strcpy-700.S | 6 ++-- + arch/arc/lib/strlen.S | 6 ++-- + arch/arc/mm/tlbex.S | 10 +++---- + 11 files changed, 54 insertions(+), 70 deletions(-) + +--- a/arch/arc/include/asm/linkage.h ++++ b/arch/arc/include/asm/linkage.h +@@ -13,20 +13,6 @@ + + #define ASM_NL ` /* use '`' to mark new line in macro */ + +-/* Can't use the ENTRY macro in linux/linkage.h +- * gas considers ';' as comment vs. newline +- */ +-.macro ARC_ENTRY name +- .global \name +- .align 4 +- \name: +-.endm +- +-.macro ARC_EXIT name +-#define ASM_PREV_SYM_ADDR(name) .-##name +- .size \ name, ASM_PREV_SYM_ADDR(\name) +-.endm +- + /* annotation for data we want in DCCM - if enabled in .config */ + .macro ARCFP_DATA nm + #ifdef CONFIG_ARC_HAS_DCCM +--- a/arch/arc/kernel/ctx_sw_asm.S ++++ b/arch/arc/kernel/ctx_sw_asm.S +@@ -62,4 +62,4 @@ __switch_to: + ld.ab blink, [sp, 4] + j [blink] + +-ARC_EXIT __switch_to ++END(__switch_to) +--- a/arch/arc/kernel/entry.S ++++ b/arch/arc/kernel/entry.S +@@ -141,7 +141,7 @@ VECTOR EV_Extension ; 0x130 + VECTOR reserved ; Reserved Exceptions + .endr + +-#include /* ARC_{EXTRY,EXIT} */ ++#include /* {EXTRY,EXIT} */ + #include /* SAVE_ALL_{INT1,INT2,SYS...} */ + #include + #include +@@ -184,7 +184,7 @@ reserved: ; processor restart + ; --------------------------------------------- + ; Level 2 ISR: Can interrupt a Level 1 ISR + ; --------------------------------------------- +-ARC_ENTRY handle_interrupt_level2 ++ENTRY(handle_interrupt_level2) + + ; TODO-vineetg for SMP this wont work + ; free up r9 as scratchpad +@@ -225,14 +225,14 @@ ARC_ENTRY handle_interrupt_level2 + + b ret_from_exception + +-ARC_EXIT handle_interrupt_level2 ++END(handle_interrupt_level2) + + #endif + + ; --------------------------------------------- + ; Level 1 ISR + ; --------------------------------------------- +-ARC_ENTRY handle_interrupt_level1 ++ENTRY(handle_interrupt_level1) + + /* free up r9 as scratchpad */ + #ifdef CONFIG_SMP +@@ -265,7 +265,7 @@ ARC_ENTRY handle_interrupt_level1 + sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg + + b ret_from_exception +-ARC_EXIT handle_interrupt_level1 ++END(handle_interrupt_level1) + + ;################### Non TLB Exception Handling ############################# + +@@ -273,7 +273,7 @@ ARC_EXIT handle_interrupt_level1 + ; Instruction Error Exception Handler + ; --------------------------------------------- + +-ARC_ENTRY instr_service ++ENTRY(instr_service) + + EXCEPTION_PROLOGUE + +@@ -284,13 +284,13 @@ ARC_ENTRY instr_service + + bl do_insterror_or_kprobe + b ret_from_exception +-ARC_EXIT instr_service ++END(instr_service) + + ; --------------------------------------------- + ; Memory Error Exception Handler + ; --------------------------------------------- + +-ARC_ENTRY mem_service ++ENTRY(mem_service) + + EXCEPTION_PROLOGUE + +@@ -301,13 +301,13 @@ ARC_ENTRY mem_service + + bl do_memory_error + b ret_from_exception +-ARC_EXIT mem_service ++END(mem_service) + + ; --------------------------------------------- + ; Machine Check Exception Handler + ; --------------------------------------------- + +-ARC_ENTRY EV_MachineCheck ++ENTRY(EV_MachineCheck) + + EXCEPTION_PROLOGUE + +@@ -331,13 +331,13 @@ ARC_ENTRY EV_MachineCheck + + j do_machine_check_fault + +-ARC_EXIT EV_MachineCheck ++END(EV_MachineCheck) + + ; --------------------------------------------- + ; Protection Violation Exception Handler + ; --------------------------------------------- + +-ARC_ENTRY EV_TLBProtV ++ENTRY(EV_TLBProtV) + + EXCEPTION_PROLOGUE + +@@ -385,12 +385,12 @@ ARC_ENTRY EV_TLBProtV + + b ret_from_exception + +-ARC_EXIT EV_TLBProtV ++END(EV_TLBProtV) + + ; --------------------------------------------- + ; Privilege Violation Exception Handler + ; --------------------------------------------- +-ARC_ENTRY EV_PrivilegeV ++ENTRY(EV_PrivilegeV) + + EXCEPTION_PROLOGUE + +@@ -401,12 +401,12 @@ ARC_ENTRY EV_PrivilegeV + + bl do_privilege_fault + b ret_from_exception +-ARC_EXIT EV_PrivilegeV ++END(EV_PrivilegeV) + + ; --------------------------------------------- + ; Extension Instruction Exception Handler + ; --------------------------------------------- +-ARC_ENTRY EV_Extension ++ENTRY(EV_Extension) + + EXCEPTION_PROLOGUE + +@@ -417,7 +417,7 @@ ARC_ENTRY EV_Extension + + bl do_extension_fault + b ret_from_exception +-ARC_EXIT EV_Extension ++END(EV_Extension) + + ;######################### System Call Tracing ######################### + +@@ -504,7 +504,7 @@ trap_with_param: + ; (2) Break Points + ;------------------------------------------------------------------ + +-ARC_ENTRY EV_Trap ++ENTRY(EV_Trap) + + EXCEPTION_PROLOGUE + +@@ -534,9 +534,9 @@ ARC_ENTRY EV_Trap + jl [r9] ; Entry into Sys Call Handler + + ; fall through to ret_from_system_call +-ARC_EXIT EV_Trap ++END(EV_Trap) + +-ARC_ENTRY ret_from_system_call ++ENTRY(ret_from_system_call) + + st r0, [sp, PT_r0] ; sys call return value in pt_regs + +@@ -546,7 +546,7 @@ ARC_ENTRY ret_from_system_call + ; + ; If ret to user mode do we need to handle signals, schedule() et al. + +-ARC_ENTRY ret_from_exception ++ENTRY(ret_from_exception) + + ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32 + ld r8, [sp, PT_status32] ; returning to User/Kernel Mode +@@ -728,9 +728,9 @@ not_level1_interrupt: + debug_marker_syscall: + rtie + +-ARC_EXIT ret_from_exception ++END(ret_from_exception) + +-ARC_ENTRY ret_from_fork ++ENTRY(ret_from_fork) + ; when the forked child comes here from the __switch_to function + ; r0 has the last task pointer. + ; put last task in scheduler queue +@@ -747,11 +747,11 @@ ARC_ENTRY ret_from_fork + ; special case of kernel_thread entry point returning back due to + ; kernel_execve() - pretend return from syscall to ret to userland + b ret_from_exception +-ARC_EXIT ret_from_fork ++END(ret_from_fork) + + ;################### Special Sys Call Wrappers ########################## + +-ARC_ENTRY sys_clone_wrapper ++ENTRY(sys_clone_wrapper) + SAVE_CALLEE_SAVED_USER + bl @sys_clone + DISCARD_CALLEE_SAVED_USER +@@ -761,7 +761,7 @@ ARC_ENTRY sys_clone_wrapper + bnz tracesys_exit + + b ret_from_system_call +-ARC_EXIT sys_clone_wrapper ++END(sys_clone_wrapper) + + #ifdef CONFIG_ARC_DW2_UNWIND + ; Workaround for bug 94179 (STAR ): +--- a/arch/arc/lib/memcmp.S ++++ b/arch/arc/lib/memcmp.S +@@ -6,7 +6,7 @@ + * published by the Free Software Foundation. + */ + +-#include ++#include + + #ifdef __LITTLE_ENDIAN__ + #define WORD2 r2 +@@ -16,7 +16,7 @@ + #define SHIFT r2 + #endif + +-ARC_ENTRY memcmp ++ENTRY(memcmp) + or r12,r0,r1 + asl_s r12,r12,30 + sub r3,r2,1 +@@ -121,4 +121,4 @@ ARC_ENTRY memcmp + .Lnil: + j_s.d [blink] + mov r0,0 +-ARC_EXIT memcmp ++END(memcmp) +--- a/arch/arc/lib/memcpy-700.S ++++ b/arch/arc/lib/memcpy-700.S +@@ -6,9 +6,9 @@ + * published by the Free Software Foundation. + */ + +-#include ++#include + +-ARC_ENTRY memcpy ++ENTRY(memcpy) + or r3,r0,r1 + asl_s r3,r3,30 + mov_s r5,r0 +@@ -63,4 +63,4 @@ ARC_ENTRY memcpy + .Lendbloop: + j_s.d [blink] + stb r12,[r5,0] +-ARC_EXIT memcpy ++END(memcpy) +--- a/arch/arc/lib/memset.S ++++ b/arch/arc/lib/memset.S +@@ -6,11 +6,11 @@ + * published by the Free Software Foundation. + */ + +-#include ++#include + + #define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ + +-ARC_ENTRY memset ++ENTRY(memset) + mov_s r4,r0 + or r12,r0,r2 + bmsk.f r12,r12,1 +@@ -46,14 +46,14 @@ ARC_ENTRY memset + stb.ab r1,[r4,1] + .Ltiny_end: + j_s [blink] +-ARC_EXIT memset ++END(memset) + + ; memzero: @r0 = mem, @r1 = size_t + ; memset: @r0 = mem, @r1 = char, @r2 = size_t + +-ARC_ENTRY memzero ++ENTRY(memzero) + ; adjust bzero args to memset args + mov r2, r1 + mov r1, 0 + b memset ;tail call so need to tinker with blink +-ARC_EXIT memzero ++END(memzero) +--- a/arch/arc/lib/strchr-700.S ++++ b/arch/arc/lib/strchr-700.S +@@ -11,9 +11,9 @@ + presence of the norm instruction makes it easier to operate on whole + words branch-free. */ + +-#include ++#include + +-ARC_ENTRY strchr ++ENTRY(strchr) + extb_s r1,r1 + asl r5,r1,8 + bmsk r2,r0,1 +@@ -130,4 +130,4 @@ ARC_ENTRY strchr + j_s.d [blink] + mov.mi r0,0 + #endif /* ENDIAN */ +-ARC_EXIT strchr ++END(strchr) +--- a/arch/arc/lib/strcmp.S ++++ b/arch/arc/lib/strcmp.S +@@ -13,9 +13,9 @@ + source 1; however, that would increase the overhead for loop setup / finish, + and strcmp might often terminate early. */ + +-#include ++#include + +-ARC_ENTRY strcmp ++ENTRY(strcmp) + or r2,r0,r1 + bmsk_s r2,r2,1 + brne r2,0,.Lcharloop +@@ -93,4 +93,4 @@ ARC_ENTRY strcmp + .Lcmpend: + j_s.d [blink] + sub r0,r2,r3 +-ARC_EXIT strcmp ++END(strcmp) +--- a/arch/arc/lib/strcpy-700.S ++++ b/arch/arc/lib/strcpy-700.S +@@ -16,9 +16,9 @@ + there, but the it is not likely to be taken often, and it + would also be likey to cost an unaligned mispredict at the next call. */ + +-#include ++#include + +-ARC_ENTRY strcpy ++ENTRY(strcpy) + or r2,r0,r1 + bmsk_s r2,r2,1 + brne.d r2,0,charloop +@@ -67,4 +67,4 @@ charloop: + brne.d r3,0,charloop + stb.ab r3,[r10,1] + j [blink] +-ARC_EXIT strcpy ++END(strcpy) +--- a/arch/arc/lib/strlen.S ++++ b/arch/arc/lib/strlen.S +@@ -6,9 +6,9 @@ + * published by the Free Software Foundation. + */ + +-#include ++#include + +-ARC_ENTRY strlen ++ENTRY(strlen) + or r3,r0,7 + ld r2,[r3,-7] + ld.a r6,[r3,-3] +@@ -80,4 +80,4 @@ ARC_ENTRY strlen + .Learly_end: + b.d .Lend + sub_s.ne r1,r1,r1 +-ARC_EXIT strlen ++END(strlen) +--- a/arch/arc/mm/tlbex.S ++++ b/arch/arc/mm/tlbex.S +@@ -260,7 +260,7 @@ ARCFP_CODE ;Fast Path Code, candidate fo + ; I-TLB Miss Exception Handler + ;----------------------------------------------------------------------------- + +-ARC_ENTRY EV_TLBMissI ++ENTRY(EV_TLBMissI) + + TLBMISS_FREEUP_REGS + +@@ -293,13 +293,13 @@ ARC_ENTRY EV_TLBMissI + TLBMISS_RESTORE_REGS + rtie + +-ARC_EXIT EV_TLBMissI ++END(EV_TLBMissI) + + ;----------------------------------------------------------------------------- + ; D-TLB Miss Exception Handler + ;----------------------------------------------------------------------------- + +-ARC_ENTRY EV_TLBMissD ++ENTRY(EV_TLBMissD) + + TLBMISS_FREEUP_REGS + +@@ -381,6 +381,4 @@ do_slow_path_pf: + bl do_page_fault + b ret_from_exception + +-ARC_EXIT EV_TLBMissD +- +-ARC_ENTRY EV_TLBMissB ; Bogus entry to measure sz of DTLBMiss hdlr ++END(EV_TLBMissD) diff --git a/queue-3.14/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch b/queue-3.14/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch new file mode 100644 index 00000000000..81df325f82d --- /dev/null +++ b/queue-3.14/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch @@ -0,0 +1,40 @@ +From add284a3a2481e759d6bec35f6444c32c8ddc383 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:32 +0000 +Subject: drm/i915: Force the CS stall for invalidate flushes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit add284a3a2481e759d6bec35f6444c32c8ddc383 upstream. + +In order to act as a full command barrier by itself, we need to tell the +pipecontrol to actually stall the command streamer while the flush runs. +We require the full command barrier before operations like +MI_SET_CONTEXT, which currently rely on a prior invalidate flush. + +References: https://bugs.freedesktop.org/show_bug.cgi?id=83677 +Cc: Simon Farnsworth +Cc: Daniel Vetter +Cc: Ville Syrjälä +Signed-off-by: Chris Wilson +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -341,6 +341,8 @@ gen7_render_ring_flush(struct intel_ring + flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + ++ flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; ++ + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ diff --git a/queue-3.14/drm-i915-invalidate-media-caches-on-gen7.patch b/queue-3.14/drm-i915-invalidate-media-caches-on-gen7.patch new file mode 100644 index 00000000000..de496014034 --- /dev/null +++ b/queue-3.14/drm-i915-invalidate-media-caches-on-gen7.patch @@ -0,0 +1,50 @@ +From 148b83d0815a3778c8949e6a97cb798cbaa0efb3 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:31 +0000 +Subject: drm/i915: Invalidate media caches on gen7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 148b83d0815a3778c8949e6a97cb798cbaa0efb3 upstream. + +In the gen7 pipe control there is an extra bit to flush the media +caches, so let's set it during cache invalidation flushes. + +v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec. + +Cc: Simon Farnsworth +Cc: Ville Syrjälä +Cc: Daniel Vetter +Signed-off-by: Chris Wilson +Reviewed-by: Daniel Vetter +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 1 + + drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -320,6 +320,7 @@ + #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ + #define PIPE_CONTROL_CS_STALL (1<<20) + #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) ++#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) + #define PIPE_CONTROL_QW_WRITE (1<<14) + #define PIPE_CONTROL_DEPTH_STALL (1<<13) + #define PIPE_CONTROL_WRITE_FLUSH (1<<12) +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -334,6 +334,7 @@ gen7_render_ring_flush(struct intel_ring + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; ++ flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; + /* + * TLB invalidate requires a post-sync write. + */ diff --git a/queue-3.14/drm-nv4c-mc-disable-msi.patch b/queue-3.14/drm-nv4c-mc-disable-msi.patch new file mode 100644 index 00000000000..03be22c11c4 --- /dev/null +++ b/queue-3.14/drm-nv4c-mc-disable-msi.patch @@ -0,0 +1,46 @@ +From 4761703bd04bbdf56396d264903cc5a1fdcb3c01 Mon Sep 17 00:00:00 2001 +From: Ilia Mirkin +Date: Tue, 16 Dec 2014 13:55:38 -0500 +Subject: drm/nv4c/mc: disable msi + +From: Ilia Mirkin + +commit 4761703bd04bbdf56396d264903cc5a1fdcb3c01 upstream. + +Several users have, over time, reported issues with MSI on these IGPs. +They're old, rarely available, and MSI doesn't provide such huge +advantages on them. Just disable. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87361 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74492 +Fixes: fa8c9ac72fe ("drm/nv4c/mc: nv4x igp's have a different msi rearm register") +Signed-off-by: Ilia Mirkin +Signed-off-by: Ben Skeggs +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c | 8 -------- + 1 file changed, 8 deletions(-) + +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c ++++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c +@@ -24,13 +24,6 @@ + + #include "nv04.h" + +-static void +-nv4c_mc_msi_rearm(struct nouveau_mc *pmc) +-{ +- struct nv04_mc_priv *priv = (void *)pmc; +- nv_wr08(priv, 0x088050, 0xff); +-} +- + struct nouveau_oclass * + nv4c_mc_oclass = &(struct nouveau_mc_oclass) { + .base.handle = NV_SUBDEV(MC, 0x4c), +@@ -41,5 +34,4 @@ nv4c_mc_oclass = &(struct nouveau_mc_ocl + .fini = _nouveau_mc_fini, + }, + .intr = nv04_mc_intr, +- .msi_rearm = nv4c_mc_msi_rearm, + }.base; diff --git a/queue-3.14/series b/queue-3.14/series index 4c980184eea..5c63d00a5d9 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -21,3 +21,8 @@ drm-radeon-check-the-right-ring-in-radeon_evict_flags.patch drm-radeon-properly-filter-dp1.2-4k-modes-on-non-dp1.2-hw.patch drm-i915-don-t-complain-about-stolen-conflicts-on-gen3.patch drm-i915-only-warn-the-first-time-we-attempt-to-mmio-whilst-suspended.patch +drm-nv4c-mc-disable-msi.patch +drm-i915-invalidate-media-caches-on-gen7.patch +drm-i915-force-the-cs-stall-for-invalidate-flushes.patch +arc-move-peripherals-to-match-model-to-fpga.patch +arc-switch-to-generic-entry-end-assembler-annotations.patch