From: Greg Kroah-Hartman Date: Sun, 20 Oct 2024 09:35:02 +0000 (+0200) Subject: 6.11-stable patches X-Git-Tag: v5.10.228~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0a50a7d0a1bd10f3db8f416ca2247cff6cd5e93c;p=thirdparty%2Fkernel%2Fstable-queue.git 6.11-stable patches added patches: drm-amdgpu-mes-fix-issue-of-writing-to-the-same-log-buffer-from-2-mes-pipes.patch drm-amdgpu-prevent-bo_handles-error-from-being-overwritten.patch drm-amdgpu-smu13-always-apply-the-powersave-optimization.patch drm-amdgpu-swsmu-only-force-workload-setup-on-init.patch drm-i915-dp_mst-don-t-require-dsc-hblank-quirk-for-a-non-dsc-compatible-mode.patch drm-i915-dp_mst-handle-error-during-dsc-bw-overhead-slice-calculation.patch drm-vmwgfx-cleanup-kms-setup-without-3d.patch drm-vmwgfx-handle-surface-check-failure-correctly.patch drm-xe-ufence-ufence-can-be-signaled-right-after-wait_woken.patch drm-xe-xe_sync-initialise-ufence.signalled.patch --- diff --git a/queue-6.11/drm-amdgpu-mes-fix-issue-of-writing-to-the-same-log-buffer-from-2-mes-pipes.patch b/queue-6.11/drm-amdgpu-mes-fix-issue-of-writing-to-the-same-log-buffer-from-2-mes-pipes.patch new file mode 100644 index 00000000000..b2c442c1606 --- /dev/null +++ b/queue-6.11/drm-amdgpu-mes-fix-issue-of-writing-to-the-same-log-buffer-from-2-mes-pipes.patch @@ -0,0 +1,42 @@ +From 7760d7f93c764625fedca176891238675fd06d62 Mon Sep 17 00:00:00 2001 +From: Michael Chen +Date: Tue, 8 Oct 2024 15:29:50 -0400 +Subject: drm/amdgpu/mes: fix issue of writing to the same log buffer from 2 MES pipes + +From: Michael Chen + +commit 7760d7f93c764625fedca176891238675fd06d62 upstream. + +With Unified MES enabled in gfx12, need separate event log buffer for the +2 MES pipes to avoid data overwrite. + +Signed-off-by: Michael Chen +Reviewed-by: Jack Xiao +Signed-off-by: Alex Deucher +(cherry picked from commit 144df260f3daab42c4611021f929b3342de516e5) +Cc: stable@vger.kernel.org # 6.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +@@ -595,7 +595,7 @@ static int mes_v12_0_set_hw_resources(st + + if (amdgpu_mes_log_enable) { + mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; +- mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; ++ mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE; + } + + return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, +@@ -1270,7 +1270,7 @@ static int mes_v12_0_sw_init(void *handl + adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; + adev->mes.enable_legacy_queue_map = true; + +- adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; ++ adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE; + + r = amdgpu_mes_init(adev); + if (r) diff --git a/queue-6.11/drm-amdgpu-prevent-bo_handles-error-from-being-overwritten.patch b/queue-6.11/drm-amdgpu-prevent-bo_handles-error-from-being-overwritten.patch new file mode 100644 index 00000000000..4940c0d82c1 --- /dev/null +++ b/queue-6.11/drm-amdgpu-prevent-bo_handles-error-from-being-overwritten.patch @@ -0,0 +1,40 @@ +From c0ec082f10b7a1fd25e8c1e2a686440da913b7a3 Mon Sep 17 00:00:00 2001 +From: Mohammed Anees +Date: Wed, 9 Oct 2024 17:58:31 +0530 +Subject: drm/amdgpu: prevent BO_HANDLES error from being overwritten +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mohammed Anees + +commit c0ec082f10b7a1fd25e8c1e2a686440da913b7a3 upstream. + +Before this patch, if multiple BO_HANDLES chunks were submitted, +the error -EINVAL would be correctly set but could be overwritten +by the return value from amdgpu_cs_p1_bo_handles(). This patch +ensures that if there are multiple BO_HANDLES, we stop. + +Fixes: fec5f8e8c6bc ("drm/amdgpu: disallow multiple BO_HANDLES chunks in one submit") +Signed-off-by: Mohammed Anees +Reviewed-by: Christian König +Signed-off-by: Pierre-Eric Pelloux-Prayer +Signed-off-by: Alex Deucher +(cherry picked from commit 40f2cd98828f454bdc5006ad3d94330a5ea164b7) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -265,7 +265,7 @@ static int amdgpu_cs_pass1(struct amdgpu + + /* Only a single BO list is allowed to simplify handling. */ + if (p->bo_list) +- ret = -EINVAL; ++ goto free_partial_kdata; + + ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata); + if (ret) diff --git a/queue-6.11/drm-amdgpu-smu13-always-apply-the-powersave-optimization.patch b/queue-6.11/drm-amdgpu-smu13-always-apply-the-powersave-optimization.patch new file mode 100644 index 00000000000..daad5161078 --- /dev/null +++ b/queue-6.11/drm-amdgpu-smu13-always-apply-the-powersave-optimization.patch @@ -0,0 +1,54 @@ +From 7a1613e47e65ba6967085ad99dee95420346a0ce Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 3 Oct 2024 10:09:50 -0400 +Subject: drm/amdgpu/smu13: always apply the powersave optimization + +From: Alex Deucher + +commit 7a1613e47e65ba6967085ad99dee95420346a0ce upstream. + +It can avoid margin issues in some very demanding applications. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3618 +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3131 +Fixes: c50fe289ed72 ("drm/amdgpu/swsmu: always force a state reprogram on init") +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +(cherry picked from commit 62f38b4ccaa6aa063ca781d80b10aacd39dc5c76) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 22 ++++++++----------- + 1 file changed, 10 insertions(+), 12 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2555,18 +2555,16 @@ static int smu_v13_0_0_set_power_profile + workload_mask = 1 << workload_type; + + /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */ +- if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { +- if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && +- ((smu->adev->pm.fw_version == 0x004e6601) || +- (smu->adev->pm.fw_version >= 0x004e7300))) || +- (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && +- smu->adev->pm.fw_version >= 0x00504500)) { +- workload_type = smu_cmn_to_asic_specific_index(smu, +- CMN2ASIC_MAPPING_WORKLOAD, +- PP_SMC_POWER_PROFILE_POWERSAVING); +- if (workload_type >= 0) +- workload_mask |= 1 << workload_type; +- } ++ if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && ++ ((smu->adev->pm.fw_version == 0x004e6601) || ++ (smu->adev->pm.fw_version >= 0x004e7300))) || ++ (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && ++ smu->adev->pm.fw_version >= 0x00504500)) { ++ workload_type = smu_cmn_to_asic_specific_index(smu, ++ CMN2ASIC_MAPPING_WORKLOAD, ++ PP_SMC_POWER_PROFILE_POWERSAVING); ++ if (workload_type >= 0) ++ workload_mask |= 1 << workload_type; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, diff --git a/queue-6.11/drm-amdgpu-swsmu-only-force-workload-setup-on-init.patch b/queue-6.11/drm-amdgpu-swsmu-only-force-workload-setup-on-init.patch new file mode 100644 index 00000000000..4945c31793f --- /dev/null +++ b/queue-6.11/drm-amdgpu-swsmu-only-force-workload-setup-on-init.patch @@ -0,0 +1,53 @@ +From cb07c8338fc2b9d5f949a19d4a07ee4d5ecf8793 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 2 Oct 2024 10:22:30 -0400 +Subject: drm/amdgpu/swsmu: Only force workload setup on init + +From: Alex Deucher + +commit cb07c8338fc2b9d5f949a19d4a07ee4d5ecf8793 upstream. + +Needed to set the workload type at init time so that +we can apply the navi3x margin optimization. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3618 +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3131 +Fixes: c50fe289ed72 ("drm/amdgpu/swsmu: always force a state reprogram on init") +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +(cherry picked from commit 580ad7cbd4b7be8d2cb5ab5c1fca6bb76045eb0e) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -2226,7 +2226,7 @@ static int smu_bump_power_profile_mode(s + static int smu_adjust_power_state_dynamic(struct smu_context *smu, + enum amd_dpm_forced_level level, + bool skip_display_settings, +- bool force_update) ++ bool init) + { + int ret = 0; + int index = 0; +@@ -2255,7 +2255,7 @@ static int smu_adjust_power_state_dynami + } + } + +- if (force_update || smu_dpm_ctx->dpm_level != level) { ++ if (smu_dpm_ctx->dpm_level != level) { + ret = smu_asic_set_performance_level(smu, level); + if (ret) { + dev_err(smu->adev->dev, "Failed to set performance level!"); +@@ -2272,7 +2272,7 @@ static int smu_adjust_power_state_dynami + index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; + workload[0] = smu->workload_setting[index]; + +- if (force_update || smu->power_profile_mode != workload[0]) ++ if (init || smu->power_profile_mode != workload[0]) + smu_bump_power_profile_mode(smu, workload, 0); + } + diff --git a/queue-6.11/drm-i915-dp_mst-don-t-require-dsc-hblank-quirk-for-a-non-dsc-compatible-mode.patch b/queue-6.11/drm-i915-dp_mst-don-t-require-dsc-hblank-quirk-for-a-non-dsc-compatible-mode.patch new file mode 100644 index 00000000000..837051b78a1 --- /dev/null +++ b/queue-6.11/drm-i915-dp_mst-don-t-require-dsc-hblank-quirk-for-a-non-dsc-compatible-mode.patch @@ -0,0 +1,37 @@ +From 2f54e71359eb2abc0bdf6619cd356e5e350ff27b Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Wed, 9 Oct 2024 14:01:35 +0300 +Subject: drm/i915/dp_mst: Don't require DSC hblank quirk for a non-DSC compatible mode + +From: Imre Deak + +commit 2f54e71359eb2abc0bdf6619cd356e5e350ff27b upstream. + +If an MST branch device doesn't support DSC for a given mode, but the +MST link has enough BW for the mode, assume that the branch device does +support the mode using an uncompressed stream. + +Fixes: 55eaef164174 ("drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk") +Cc: stable@vger.kernel.org # v6.8+ +Reviewed-by: Suraj Kandpal +Signed-off-by: Imre Deak +Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-2-imre.deak@intel.com +(cherry picked from commit 4e75c3e208a06ad6fd9b3517fb77337460d7c2b0) +Signed-off-by: Joonas Lahtinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c +@@ -465,6 +465,9 @@ hblank_expansion_quirk_needs_dsc(const s + if (mode_hblank_period_ns(adjusted_mode) > hblank_limit) + return false; + ++ if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state)) ++ return false; ++ + return true; + } + diff --git a/queue-6.11/drm-i915-dp_mst-handle-error-during-dsc-bw-overhead-slice-calculation.patch b/queue-6.11/drm-i915-dp_mst-handle-error-during-dsc-bw-overhead-slice-calculation.patch new file mode 100644 index 00000000000..5ba2747ed78 --- /dev/null +++ b/queue-6.11/drm-i915-dp_mst-handle-error-during-dsc-bw-overhead-slice-calculation.patch @@ -0,0 +1,110 @@ +From 69b3d87212676c4c22aa4660435e2066dc7d1311 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Wed, 9 Oct 2024 14:01:34 +0300 +Subject: drm/i915/dp_mst: Handle error during DSC BW overhead/slice calculation + +From: Imre Deak + +commit 69b3d87212676c4c22aa4660435e2066dc7d1311 upstream. + +The MST branch device may not support the number of DSC slices a mode +requires, handle the error in this case. + +Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation") +Cc: stable@vger.kernel.org # v6.8+ +Reviewed-by: Suraj Kandpal +Signed-off-by: Imre Deak +Link: https://patchwork.freedesktop.org/patch/msgid/20241009110135.1216498-1-imre.deak@intel.com +(cherry picked from commit 802a69b6b8a0502a9e2309afec7e1b77f67874f2) +Signed-off-by: Joonas Lahtinen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp_mst.c | 37 ++++++++++++++++++++-------- + 1 file changed, 27 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c +@@ -88,25 +88,19 @@ static int intel_dp_mst_max_dpt_bpp(cons + + static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, + const struct intel_connector *connector, +- bool ssc, bool dsc, int bpp_x16) ++ bool ssc, int dsc_slice_count, int bpp_x16) + { + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + unsigned long flags = DRM_DP_BW_OVERHEAD_MST; +- int dsc_slice_count = 0; + int overhead; + + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; + +- if (dsc) { ++ if (dsc_slice_count) + flags |= DRM_DP_BW_OVERHEAD_DSC; +- dsc_slice_count = intel_dp_dsc_get_slice_count(connector, +- adjusted_mode->clock, +- adjusted_mode->hdisplay, +- crtc_state->joiner_pipes); +- } + + overhead = drm_dp_bw_overhead(crtc_state->lane_count, + adjusted_mode->hdisplay, +@@ -152,6 +146,19 @@ static int intel_dp_mst_calc_pbn(int pix + return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000); + } + ++static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connector, ++ const struct intel_crtc_state *crtc_state) ++{ ++ const struct drm_display_mode *adjusted_mode = ++ &crtc_state->hw.adjusted_mode; ++ int num_joined_pipes = crtc_state->joiner_pipes; ++ ++ return intel_dp_dsc_get_slice_count(connector, ++ adjusted_mode->clock, ++ adjusted_mode->hdisplay, ++ num_joined_pipes); ++} ++ + static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + int max_bpp, +@@ -171,6 +178,7 @@ static int intel_dp_mst_find_vcpi_slots_ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int bpp, slots = -EINVAL; ++ int dsc_slice_count = 0; + int max_dpt_bpp; + int ret = 0; + +@@ -202,6 +210,15 @@ static int intel_dp_mst_find_vcpi_slots_ + drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", + min_bpp, max_bpp); + ++ if (dsc) { ++ dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state); ++ if (!dsc_slice_count) { ++ drm_dbg_kms(&i915->drm, "Can't get valid DSC slice count\n"); ++ ++ return -ENOSPC; ++ } ++ } ++ + for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { + int local_bw_overhead; + int remote_bw_overhead; +@@ -215,9 +232,9 @@ static int intel_dp_mst_find_vcpi_slots_ + intel_dp_output_bpp(crtc_state->output_format, bpp)); + + local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, +- false, dsc, link_bpp_x16); ++ false, dsc_slice_count, link_bpp_x16); + remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, +- true, dsc, link_bpp_x16); ++ true, dsc_slice_count, link_bpp_x16); + + intel_dp_mst_compute_m_n(crtc_state, connector, + local_bw_overhead, diff --git a/queue-6.11/drm-vmwgfx-cleanup-kms-setup-without-3d.patch b/queue-6.11/drm-vmwgfx-cleanup-kms-setup-without-3d.patch new file mode 100644 index 00000000000..75bcba9b39e --- /dev/null +++ b/queue-6.11/drm-vmwgfx-cleanup-kms-setup-without-3d.patch @@ -0,0 +1,99 @@ +From 512a9721cae0d88d34ff441f2f5917cd149af8af Mon Sep 17 00:00:00 2001 +From: Zack Rusin +Date: Tue, 27 Aug 2024 00:39:05 -0400 +Subject: drm/vmwgfx: Cleanup kms setup without 3d + +From: Zack Rusin + +commit 512a9721cae0d88d34ff441f2f5917cd149af8af upstream. + +Do not validate format equality for the non 3d cases to allow xrgb to +argb copies and make sure the dx binding flags are only used +on dx compatible surfaces. + +Fixes basic 2d kms setup on configurations without 3d. There's little +practical benefit to it because kms framebuffer coherence is disabled +on configurations without 3d but with those changes the code actually +makes sense. + +v2: Remove the now unused format variable + +Signed-off-by: Zack Rusin +Fixes: d6667f0ddf46 ("drm/vmwgfx: Fix handling of dumb buffers") +Cc: Broadcom internal kernel review list +Cc: dri-devel@lists.freedesktop.org +Cc: # v6.9+ +Cc: Maaz Mombasawala +Cc: Martin Krastev +Reviewed-by: Martin Krastev +Reviewed-by: Maaz Mombasawala +Link: https://patchwork.freedesktop.org/patch/msgid/20240827043905.472825-1-zack.rusin@broadcom.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 29 ----------------------------- + drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 9 ++++++--- + 2 files changed, 6 insertions(+), 32 deletions(-) + +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +@@ -1283,7 +1283,6 @@ static int vmw_kms_new_framebuffer_surfa + { + struct drm_device *dev = &dev_priv->drm; + struct vmw_framebuffer_surface *vfbs; +- enum SVGA3dSurfaceFormat format; + struct vmw_surface *surface; + int ret; + +@@ -1320,34 +1319,6 @@ static int vmw_kms_new_framebuffer_surfa + return -EINVAL; + } + +- switch (mode_cmd->pixel_format) { +- case DRM_FORMAT_ARGB8888: +- format = SVGA3D_A8R8G8B8; +- break; +- case DRM_FORMAT_XRGB8888: +- format = SVGA3D_X8R8G8B8; +- break; +- case DRM_FORMAT_RGB565: +- format = SVGA3D_R5G6B5; +- break; +- case DRM_FORMAT_XRGB1555: +- format = SVGA3D_A1R5G5B5; +- break; +- default: +- DRM_ERROR("Invalid pixel format: %p4cc\n", +- &mode_cmd->pixel_format); +- return -EINVAL; +- } +- +- /* +- * For DX, surface format validation is done when surface->scanout +- * is set. +- */ +- if (!has_sm4_context(dev_priv) && format != surface->metadata.format) { +- DRM_ERROR("Invalid surface format for requested mode.\n"); +- return -EINVAL; +- } +- + vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL); + if (!vfbs) { + ret = -ENOMEM; +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +@@ -2276,9 +2276,12 @@ int vmw_dumb_create(struct drm_file *fil + const struct SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format); + SVGA3dSurfaceAllFlags flags = SVGA3D_SURFACE_HINT_TEXTURE | + SVGA3D_SURFACE_HINT_RENDERTARGET | +- SVGA3D_SURFACE_SCREENTARGET | +- SVGA3D_SURFACE_BIND_SHADER_RESOURCE | +- SVGA3D_SURFACE_BIND_RENDER_TARGET; ++ SVGA3D_SURFACE_SCREENTARGET; ++ ++ if (vmw_surface_is_dx_screen_target_format(format)) { ++ flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE | ++ SVGA3D_SURFACE_BIND_RENDER_TARGET; ++ } + + /* + * Without mob support we're just going to use raw memory buffer diff --git a/queue-6.11/drm-vmwgfx-handle-surface-check-failure-correctly.patch b/queue-6.11/drm-vmwgfx-handle-surface-check-failure-correctly.patch new file mode 100644 index 00000000000..a6508f1269c --- /dev/null +++ b/queue-6.11/drm-vmwgfx-handle-surface-check-failure-correctly.patch @@ -0,0 +1,37 @@ +From 26498b8d54373d31a621d7dec95c4bd842563b3b Mon Sep 17 00:00:00 2001 +From: Nikolay Kuratov +Date: Wed, 2 Oct 2024 15:24:29 +0300 +Subject: drm/vmwgfx: Handle surface check failure correctly + +From: Nikolay Kuratov + +commit 26498b8d54373d31a621d7dec95c4bd842563b3b upstream. + +Currently if condition (!bo and !vmw_kms_srf_ok()) was met +we go to err_out with ret == 0. +err_out dereferences vfb if ret == 0, but in our case vfb is still NULL. + +Fix this by assigning sensible error to ret. + +Found by Linux Verification Center (linuxtesting.org) with SVACE + +Signed-off-by: Nikolay Kuratov +Cc: stable@vger.kernel.org +Fixes: 810b3e1683d0 ("drm/vmwgfx: Support topology greater than texture size") +Signed-off-by: Zack Rusin +Link: https://patchwork.freedesktop.org/patch/msgid/20241002122429.1981822-1-kniv@yandex-team.ru +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +@@ -1510,6 +1510,7 @@ static struct drm_framebuffer *vmw_kms_f + DRM_ERROR("Surface size cannot exceed %dx%d\n", + dev_priv->texture_max_width, + dev_priv->texture_max_height); ++ ret = -EINVAL; + goto err_out; + } + diff --git a/queue-6.11/drm-xe-ufence-ufence-can-be-signaled-right-after-wait_woken.patch b/queue-6.11/drm-xe-ufence-ufence-can-be-signaled-right-after-wait_woken.patch new file mode 100644 index 00000000000..46e74650ee6 --- /dev/null +++ b/queue-6.11/drm-xe-ufence-ufence-can-be-signaled-right-after-wait_woken.patch @@ -0,0 +1,49 @@ +From 4e8b5a165160e2f521cc10bae58ce0b72b2e22b5 Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Fri, 11 Oct 2024 17:10:29 +0200 +Subject: drm/xe/ufence: ufence can be signaled right after wait_woken + +From: Nirmoy Das + +commit 4e8b5a165160e2f521cc10bae58ce0b72b2e22b5 upstream. + +do_comapre() can return success after a timedout wait_woken() which was +treated as -ETIME. The loop calling wait_woken() sets correct err so +there is no need to re-evaluate err. + +v2: Remove entire check that reevaluate err at the end(Matt) + +Fixes: e670f0b4ef24 ("drm/xe/uapi: Return correct error code for xe_wait_user_fence_ioctl") +Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1630 +Cc: stable@vger.kernel.org # v6.8+ +Cc: Bommu Krishnaiah +Cc: Matthew Auld +Cc: Matthew Brost +Reviewed-by: Matthew Brost +Reviewed-by: Matthew Auld +Link: https://patchwork.freedesktop.org/patch/msgid/20241011151029.4160630-1-nirmoy.das@intel.com +Signed-off-by: Nirmoy Das +(cherry picked from commit ec7e6a1d527755fc3c7a3303eaa5577aac5cf6be) +Signed-off-by: Lucas De Marchi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_wait_user_fence.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c +index d46fa8374980..f5deb81eba01 100644 +--- a/drivers/gpu/drm/xe/xe_wait_user_fence.c ++++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c +@@ -169,9 +169,6 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data, + args->timeout = 0; + } + +- if (!timeout && !(err < 0)) +- err = -ETIME; +- + if (q) + xe_exec_queue_put(q); + +-- +2.47.0 + diff --git a/queue-6.11/drm-xe-xe_sync-initialise-ufence.signalled.patch b/queue-6.11/drm-xe-xe_sync-initialise-ufence.signalled.patch new file mode 100644 index 00000000000..349e4521adf --- /dev/null +++ b/queue-6.11/drm-xe-xe_sync-initialise-ufence.signalled.patch @@ -0,0 +1,45 @@ +From 816b186ce2e87df7c7ead4ad44f70f3b10a04c91 Mon Sep 17 00:00:00 2001 +From: Matthew Auld +Date: Fri, 11 Oct 2024 14:36:34 +0100 +Subject: drm/xe/xe_sync: initialise ufence.signalled + +From: Matthew Auld + +commit 816b186ce2e87df7c7ead4ad44f70f3b10a04c91 upstream. + +We can incorrectly think that the fence has signalled, if we get a +non-zero value here from the kmalloc, which is quite plausible. Just use +kzalloc to prevent stuff like this. + +Fixes: 977e5b82e090 ("drm/xe: Expose user fence from xe_sync_entry") +Signed-off-by: Matthew Auld +Cc: Mika Kuoppala +Cc: Matthew Brost +Cc: Nirmoy Das +Cc: # v6.10+ +Reviewed-by: Nirmoy Das +Reviewed-by: Matthew Brost +Link: https://patchwork.freedesktop.org/patch/msgid/20241011133633.388008-2-matthew.auld@intel.com +(cherry picked from commit 26f69e88dcc95fffc62ed2aea30ad7b1fdf31fdb) +Signed-off-by: Lucas De Marchi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_sync.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c +index bb3c2a830362..c6cf227ead40 100644 +--- a/drivers/gpu/drm/xe/xe_sync.c ++++ b/drivers/gpu/drm/xe/xe_sync.c +@@ -58,7 +58,7 @@ static struct xe_user_fence *user_fence_create(struct xe_device *xe, u64 addr, + if (!access_ok(ptr, sizeof(*ptr))) + return ERR_PTR(-EFAULT); + +- ufence = kmalloc(sizeof(*ufence), GFP_KERNEL); ++ ufence = kzalloc(sizeof(*ufence), GFP_KERNEL); + if (!ufence) + return ERR_PTR(-ENOMEM); + +-- +2.47.0 + diff --git a/queue-6.11/series b/queue-6.11/series index 0637db3c50a..13a68609def 100644 --- a/queue-6.11/series +++ b/queue-6.11/series @@ -57,3 +57,13 @@ scsi-ufs-core-set-sdev_offline-when-ufs-is-shut-down.patch scsi-ufs-core-fix-the-issue-of-icu-failure.patch scsi-ufs-core-requeue-aborted-request.patch drm-radeon-fix-encoder-possible_clones.patch +drm-i915-dp_mst-handle-error-during-dsc-bw-overhead-slice-calculation.patch +drm-i915-dp_mst-don-t-require-dsc-hblank-quirk-for-a-non-dsc-compatible-mode.patch +drm-xe-xe_sync-initialise-ufence.signalled.patch +drm-xe-ufence-ufence-can-be-signaled-right-after-wait_woken.patch +drm-vmwgfx-cleanup-kms-setup-without-3d.patch +drm-vmwgfx-handle-surface-check-failure-correctly.patch +drm-amdgpu-mes-fix-issue-of-writing-to-the-same-log-buffer-from-2-mes-pipes.patch +drm-amdgpu-smu13-always-apply-the-powersave-optimization.patch +drm-amdgpu-swsmu-only-force-workload-setup-on-init.patch +drm-amdgpu-prevent-bo_handles-error-from-being-overwritten.patch