From: Simon Cook <simon.cook@embecosm.com>
Date: Wed, 22 May 2019 11:59:58 +0000 (+0100)
Subject: gdb/riscv: Improve flen length determination
X-Git-Tag: binutils-2_33~1123
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0a5954bd5f96dd665cb733b9ab6f2ca67bb4632d;p=thirdparty%2Fbinutils-gdb.git

gdb/riscv: Improve flen length determination

This solves an assertion failure when a remote provides a target
description which only refers to floating point registers by their
hardware name (e.g. f0), rather than their ABI name (e.g. ft0). GDB
assumed that should the floating point register feature be presented,
it would contain a register called ft0.

The floating point length is now instead determined by searching for
the same register, but looking for any of its aliases.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_gdbarch_init): Support determining flen from
	target descriptions using exclusively floating point register name
	aliases.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index b0b7503b284..a998c5c60dc 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2019-05-22  Simon Cook  <simon.cook@embecosm.com>
+
+	* riscv-tdep.c (riscv_gdbarch_init): Support determining flen from
+	target descriptions using exclusively floating point register name
+	aliases.
+
 2019-05-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 
 	PR gdb/18644:
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 4fe07ef4375..3fc86ab8253 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3094,7 +3094,21 @@ riscv_gdbarch_init (struct gdbarch_info info,
       valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
                                             &riscv_freg_feature);
 
-      int bitsize = tdesc_register_bitsize (feature_fpu, "ft0");
+      /* Search for the first floating point register (by any alias), to
+         determine the bitsize.  */
+      int bitsize = -1;
+      const auto &fp0 = riscv_freg_feature.registers[0];
+
+      for (const char *name : fp0.names)
+	{
+	  if (tdesc_unnumbered_register (feature_fpu, name))
+	    {
+	      bitsize = tdesc_register_bitsize (feature_fpu, name);
+	      break;
+	    }
+	}
+
+      gdb_assert (bitsize != -1);
       features.flen = (bitsize / 8);
 
       if (riscv_debug_gdbarch)