From: Greg Kroah-Hartman Date: Wed, 8 Dec 2021 13:18:49 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v4.4.295~83 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0ab1d6d42323193367ea6a732e44087bbe1fda1f;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: serial-tegra-change-lower-tolerance-baud-rate-limit-for-tegra20-and-tegra30.patch --- diff --git a/queue-5.4/serial-tegra-change-lower-tolerance-baud-rate-limit-for-tegra20-and-tegra30.patch b/queue-5.4/serial-tegra-change-lower-tolerance-baud-rate-limit-for-tegra20-and-tegra30.patch new file mode 100644 index 00000000000..a97bf4e132e --- /dev/null +++ b/queue-5.4/serial-tegra-change-lower-tolerance-baud-rate-limit-for-tegra20-and-tegra30.patch @@ -0,0 +1,47 @@ +From b40de7469ef135161c80af0e8c462298cc5dac00 Mon Sep 17 00:00:00 2001 +From: Patrik John +Date: Tue, 23 Nov 2021 14:27:38 +0100 +Subject: serial: tegra: Change lower tolerance baud rate limit for tegra20 and tegra30 + +From: Patrik John + +commit b40de7469ef135161c80af0e8c462298cc5dac00 upstream. + +The current implementation uses 0 as lower limit for the baud rate +tolerance for tegra20 and tegra30 chips which causes isses on UART +initialization as soon as baud rate clock is lower than required even +when within the standard UART tolerance of +/- 4%. + +This fix aligns the implementation with the initial commit description +of +/- 4% tolerance for tegra chips other than tegra186 and +tegra194. + +Fixes: d781ec21bae6 ("serial: tegra: report clk rate errors") +Cc: stable +Signed-off-by: Patrik John +Link: https://lore.kernel.org/r/sig.19614244f8.20211123132737.88341-1-patrik.john@u-blox.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/serial-tegra.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/tty/serial/serial-tegra.c ++++ b/drivers/tty/serial/serial-tegra.c +@@ -1494,7 +1494,7 @@ static struct tegra_uart_chip_data tegra + .fifo_mode_enable_status = false, + .uart_max_port = 5, + .max_dma_burst_bytes = 4, +- .error_tolerance_low_range = 0, ++ .error_tolerance_low_range = -4, + .error_tolerance_high_range = 4, + }; + +@@ -1505,7 +1505,7 @@ static struct tegra_uart_chip_data tegra + .fifo_mode_enable_status = false, + .uart_max_port = 5, + .max_dma_burst_bytes = 4, +- .error_tolerance_low_range = 0, ++ .error_tolerance_low_range = -4, + .error_tolerance_high_range = 4, + }; + diff --git a/queue-5.4/series b/queue-5.4/series new file mode 100644 index 00000000000..7e3e7346d4f --- /dev/null +++ b/queue-5.4/series @@ -0,0 +1 @@ +serial-tegra-change-lower-tolerance-baud-rate-limit-for-tegra20-and-tegra30.patch