From: Richard Henderson <richard.henderson@linaro.org>
Date: Tue, 26 Apr 2022 16:30:31 +0000 (-0700)
Subject: target/arm: Use tcg_constant in trans_CSEL
X-Git-Tag: v7.1.0-rc0~123^2~19
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0b188ea05acb57b32604706a6f22d82121414ec9;p=thirdparty%2Fqemu.git

target/arm: Use tcg_constant in trans_CSEL

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5ce23947a17..37fb17cdaaf 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8982,13 +8982,14 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
     }
 
     /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
+    zero = tcg_constant_i32(0);
     if (a->rn == 15) {
-        rn = tcg_const_i32(0);
+        rn = zero;
     } else {
         rn = load_reg(s, a->rn);
     }
     if (a->rm == 15) {
-        rm = tcg_const_i32(0);
+        rm = zero;
     } else {
         rm = load_reg(s, a->rm);
     }
@@ -9010,10 +9011,8 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
     }
 
     arm_test_cc(&c, a->fcond);
-    zero = tcg_const_i32(0);
     tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
     arm_free_cc(&c);
-    tcg_temp_free_i32(zero);
 
     store_reg(s, a->rd, rn);
     tcg_temp_free_i32(rm);