From: Sasha Levin Date: Thu, 11 May 2023 15:48:33 +0000 (-0400) Subject: Fixes for 6.3 X-Git-Tag: v4.14.315~121 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0ba62b431a09d354537fa9a9a419dcdbe3fafd57;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.3 Signed-off-by: Sasha Levin --- diff --git a/queue-6.3/crypto-ccp-clear-psp-interrupt-status-register-befor.patch b/queue-6.3/crypto-ccp-clear-psp-interrupt-status-register-befor.patch new file mode 100644 index 00000000000..353858718bc --- /dev/null +++ b/queue-6.3/crypto-ccp-clear-psp-interrupt-status-register-befor.patch @@ -0,0 +1,74 @@ +From 087648bf7a8d2b09a60e90994be7e720c861136a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Mar 2023 15:16:36 +0000 +Subject: crypto: ccp - Clear PSP interrupt status register before calling + handler + +From: Jeremi Piotrowski + +[ Upstream commit 45121ad4a1750ca47ce3f32bd434bdb0cdbf0043 ] + +The PSP IRQ is edge-triggered (MSI or MSI-X) in all cases supported by +the psp module so clear the interrupt status register early in the +handler to prevent missed interrupts. sev_irq_handler() calls wake_up() +on a wait queue, which can result in a new command being submitted from +a different CPU. This then races with the clearing of isr and can result +in missed interrupts. A missed interrupt results in a command waiting +until it times out, which results in the psp being declared dead. + +This is unlikely on bare metal, but has been observed when running +virtualized. In the cases where this is observed, sev->cmdresp_reg has +PSP_CMDRESP_RESP set which indicates that the command was processed +correctly but no interrupt was asserted. + +The full sequence of events looks like this: + +CPU 1: submits SEV cmd #1 +CPU 1: calls wait_event_timeout() +CPU 0: enters psp_irq_handler() +CPU 0: calls sev_handler()->wake_up() +CPU 1: wakes up; finishes processing cmd #1 +CPU 1: submits SEV cmd #2 +CPU 1: calls wait_event_timeout() +PSP: finishes processing cmd #2; interrupt status is still set; no interrupt +CPU 0: clears intsts +CPU 0: exits psp_irq_handler() +CPU 1: wait_event_timeout() times out; psp_dead=true + +Fixes: 200664d5237f ("crypto: ccp: Add Secure Encrypted Virtualization (SEV) command support") +Cc: stable@vger.kernel.org +Signed-off-by: Jeremi Piotrowski +Acked-by: Tom Lendacky +Signed-off-by: Herbert Xu +Signed-off-by: Sasha Levin +--- + drivers/crypto/ccp/psp-dev.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index c9c741ac84421..949a3fa0b94a9 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -42,6 +42,9 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + /* Read the interrupt status: */ + status = ioread32(psp->io_regs + psp->vdata->intsts_reg); + ++ /* Clear the interrupt status by writing the same value we read. */ ++ iowrite32(status, psp->io_regs + psp->vdata->intsts_reg); ++ + /* invoke subdevice interrupt handlers */ + if (status) { + if (psp->sev_irq_handler) +@@ -51,9 +54,6 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + psp->tee_irq_handler(irq, psp->tee_irq_data, status); + } + +- /* Clear the interrupt status by writing the same value we read. */ +- iowrite32(status, psp->io_regs + psp->vdata->intsts_reg); +- + return IRQ_HANDLED; + } + +-- +2.39.2 + diff --git a/queue-6.3/mtd-spi-nor-add-a-rww-flag.patch b/queue-6.3/mtd-spi-nor-add-a-rww-flag.patch new file mode 100644 index 00000000000..c42ca2e58fb --- /dev/null +++ b/queue-6.3/mtd-spi-nor-add-a-rww-flag.patch @@ -0,0 +1,83 @@ +From 62e6f818ae8880ae924b119f9cb1bddb2069d42f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Mar 2023 17:41:03 +0200 +Subject: mtd: spi-nor: Add a RWW flag + +From: Miquel Raynal + +[ Upstream commit 4eddee70140b3ae183398b246a609756546c51f1 ] + +Introduce a new (no SFDP) flag for the feature that we are about to +support: Read While Write. This means, if the chip has several banks and +supports RWW, once a page of data to write has been transferred into the +chip's internal SRAM, another read operation happening on a different +bank can be performed during the tPROG delay. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/r/20230328154105.448540-7-miquel.raynal@bootlin.com +Signed-off-by: Tudor Ambarus +Stable-dep-of: 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") +Signed-off-by: Sasha Levin +--- + drivers/mtd/spi-nor/core.c | 3 +++ + drivers/mtd/spi-nor/core.h | 3 +++ + drivers/mtd/spi-nor/debugfs.c | 1 + + 3 files changed, 7 insertions(+) + +diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c +index 71ea5b2e10140..f9c226ba644ea 100644 +--- a/drivers/mtd/spi-nor/core.c ++++ b/drivers/mtd/spi-nor/core.c +@@ -2470,6 +2470,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) + + if (flags & NO_CHIP_ERASE) + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; ++ ++ if (flags & SPI_NOR_RWW) ++ nor->flags |= SNOR_F_RWW; + } + + /** +diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h +index e0cc42a4a0c84..ea128ab0ec0e0 100644 +--- a/drivers/mtd/spi-nor/core.h ++++ b/drivers/mtd/spi-nor/core.h +@@ -130,6 +130,7 @@ enum spi_nor_option_flags { + SNOR_F_IO_MODE_EN_VOLATILE = BIT(11), + SNOR_F_SOFT_RESET = BIT(12), + SNOR_F_SWP_IS_VOLATILE = BIT(13), ++ SNOR_F_RWW = BIT(14), + }; + + struct spi_nor_read_command { +@@ -459,6 +460,7 @@ struct spi_nor_fixups { + * NO_CHIP_ERASE: chip does not support chip erase. + * SPI_NOR_NO_FR: can't do fastread. + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. ++ * SPI_NOR_RWW: flash supports reads while write. + * + * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP. + * Used when SFDP tables are not defined in the flash. These +@@ -509,6 +511,7 @@ struct flash_info { + #define NO_CHIP_ERASE BIT(7) + #define SPI_NOR_NO_FR BIT(8) + #define SPI_NOR_QUAD_PP BIT(9) ++#define SPI_NOR_RWW BIT(10) + + u8 no_sfdp_flags; + #define SPI_NOR_SKIP_SFDP BIT(0) +diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c +index fc7ad203df128..7e30b94b49983 100644 +--- a/drivers/mtd/spi-nor/debugfs.c ++++ b/drivers/mtd/spi-nor/debugfs.c +@@ -25,6 +25,7 @@ static const char *const snor_f_names[] = { + SNOR_F_NAME(IO_MODE_EN_VOLATILE), + SNOR_F_NAME(SOFT_RESET), + SNOR_F_NAME(SWP_IS_VOLATILE), ++ SNOR_F_NAME(RWW), + }; + #undef SNOR_F_NAME + +-- +2.39.2 + diff --git a/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch b/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch new file mode 100644 index 00000000000..7ff45a4f5a2 --- /dev/null +++ b/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch @@ -0,0 +1,108 @@ +From a02ef8350b5e4a694b076271ce7536d0f66f6b3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Apr 2023 15:17:44 +0900 +Subject: mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx + SEMPER flash + +From: Takahiro Kuwano + +[ Upstream commit 9fd0945fe6fadfb6b54a9cd73be101c02b3e8134 ] + +Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program +granularity is 16-byte ECC data unit size. JFFS2 supports write buffer +mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE +flag in order to enable JFFS2 write buffer mode support. + +A new SNOR_F_ECC flag is introduced to determine if the part has on-die +ECC and if it has, MTD_BIT_WRITEABLE is unset. + +In vendor specific driver, a common cypress_nor_ecc_init() helper is +added. This helper takes care for ECC related initialization for SEMPER +flash family by setting up params->writesize and SNOR_F_ECC. + +Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") +Suggested-by: Tudor Ambarus +Signed-off-by: Takahiro Kuwano +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com +Signed-off-by: Tudor Ambarus +Signed-off-by: Sasha Levin +--- + drivers/mtd/spi-nor/core.c | 3 +++ + drivers/mtd/spi-nor/core.h | 1 + + drivers/mtd/spi-nor/debugfs.c | 1 + + drivers/mtd/spi-nor/spansion.c | 13 ++++++++++++- + 4 files changed, 17 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c +index f9c226ba644ea..bcc181c425de6 100644 +--- a/drivers/mtd/spi-nor/core.c ++++ b/drivers/mtd/spi-nor/core.c +@@ -2982,6 +2982,9 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) + mtd->name = dev_name(dev); + mtd->type = MTD_NORFLASH; + mtd->flags = MTD_CAP_NORFLASH; ++ /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */ ++ if (nor->flags & SNOR_F_ECC) ++ mtd->flags &= ~MTD_BIT_WRITEABLE; + if (nor->info->flags & SPI_NOR_NO_ERASE) + mtd->flags |= MTD_NO_ERASE; + else +diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h +index ea128ab0ec0e0..6eece1754ec0a 100644 +--- a/drivers/mtd/spi-nor/core.h ++++ b/drivers/mtd/spi-nor/core.h +@@ -131,6 +131,7 @@ enum spi_nor_option_flags { + SNOR_F_SOFT_RESET = BIT(12), + SNOR_F_SWP_IS_VOLATILE = BIT(13), + SNOR_F_RWW = BIT(14), ++ SNOR_F_ECC = BIT(15), + }; + + struct spi_nor_read_command { +diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c +index 7e30b94b49983..e11536fffe0f4 100644 +--- a/drivers/mtd/spi-nor/debugfs.c ++++ b/drivers/mtd/spi-nor/debugfs.c +@@ -26,6 +26,7 @@ static const char *const snor_f_names[] = { + SNOR_F_NAME(SOFT_RESET), + SNOR_F_NAME(SWP_IS_VOLATILE), + SNOR_F_NAME(RWW), ++ SNOR_F_NAME(ECC), + }; + #undef SNOR_F_NAME + +diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c +index 12a256c0ef4c6..4c34077f12162 100644 +--- a/drivers/mtd/spi-nor/spansion.c ++++ b/drivers/mtd/spi-nor/spansion.c +@@ -218,6 +218,17 @@ static int cypress_nor_set_page_size(struct spi_nor *nor) + return 0; + } + ++static void cypress_nor_ecc_init(struct spi_nor *nor) ++{ ++ /* ++ * Programming is supported only in 16-byte ECC data unit granularity. ++ * Byte-programming, bit-walking, or multiple program operations to the ++ * same ECC data unit without an erase are not allowed. ++ */ ++ nor->params->writesize = 16; ++ nor->flags |= SNOR_F_ECC; ++} ++ + static int + s25hx_t_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, +@@ -324,7 +335,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, + static void s28hx_t_late_init(struct spi_nor *nor) + { + nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; +- nor->params->writesize = 16; ++ cypress_nor_ecc_init(nor); + } + + static const struct spi_nor_fixups s28hx_t_fixups = { +-- +2.39.2 + diff --git a/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch-29548 b/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch-29548 new file mode 100644 index 00000000000..798f029e5d2 --- /dev/null +++ b/queue-6.3/mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch-29548 @@ -0,0 +1,49 @@ +From f95e0b1553bf1de50585d3f7e943a168d699b7f9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Apr 2023 15:17:45 +0900 +Subject: mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx + SEMPER flash + +From: Takahiro Kuwano + +[ Upstream commit 4199c1719e24e73be0acc8b0146fc31ad8af9771 ] + +Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program +granularity is 16-byte ECC data unit size. JFFS2 supports write buffer +mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE +flag in order to enable JFFS2 write buffer mode support. + +Fixes: b6b23833fc42 ("mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups") +Suggested-by: Tudor Ambarus +Signed-off-by: Takahiro Kuwano +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/a1cc128e094db4ec141f85bd380127598dfef17e.1680760742.git.Takahiro.Kuwano@infineon.com +Signed-off-by: Tudor Ambarus +Signed-off-by: Sasha Levin +--- + drivers/mtd/spi-nor/spansion.c | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c +index 4c34077f12162..27a3634762ad3 100644 +--- a/drivers/mtd/spi-nor/spansion.c ++++ b/drivers/mtd/spi-nor/spansion.c +@@ -266,13 +266,10 @@ static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor) + + static void s25hx_t_late_init(struct spi_nor *nor) + { +- struct spi_nor_flash_parameter *params = nor->params; +- + /* Fast Read 4B requires mode cycles */ +- params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; ++ nor->params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; + +- /* The writesize should be ECC data unit size */ +- params->writesize = 16; ++ cypress_nor_ecc_init(nor); + } + + static struct spi_nor_fixups s25hx_t_fixups = { +-- +2.39.2 + diff --git a/queue-6.3/qcom-llcc-edac-support-polling-mode-for-ecc-handling.patch b/queue-6.3/qcom-llcc-edac-support-polling-mode-for-ecc-handling.patch new file mode 100644 index 00000000000..05173aa11c8 --- /dev/null +++ b/queue-6.3/qcom-llcc-edac-support-polling-mode-for-ecc-handling.patch @@ -0,0 +1,147 @@ +From e9d6a18de84eae08bb39c3653c52a2518826fc0e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 14 Mar 2023 13:34:42 +0530 +Subject: qcom: llcc/edac: Support polling mode for ECC handling + +From: Manivannan Sadhasivam + +[ Upstream commit 721d3e91bfc93975c5e1a76c7d588dd8df5d82da ] + +Not all Qcom platforms support IRQ mode for ECC handling. For those +platforms, the current EDAC driver will not be probed due to missing ECC +IRQ in devicetree. + +So add support for polling mode so that the EDAC driver can be used on all +Qcom platforms supporting LLCC. + +The polling delay of 5000ms is chosen based on Qcom downstream/vendor +driver. + +Reported-by: Luca Weiss +Tested-by: Luca Weiss +Tested-by: Steev Klimaszewski # Thinkpad X13s +Tested-by: Andrew Halaney # sa8540p-ride +Reviewed-by: Borislav Petkov (AMD) +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230314080443.64635-14-manivannan.sadhasivam@linaro.org +Stable-dep-of: cca94f1dd6d0 ("soc: qcom: llcc: Do not create EDAC platform device on SDM845") +Signed-off-by: Sasha Levin +--- + drivers/edac/qcom_edac.c | 50 +++++++++++++++++++++--------------- + drivers/soc/qcom/llcc-qcom.c | 13 +++++----- + 2 files changed, 35 insertions(+), 28 deletions(-) + +diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c +index 3256254c3722c..a7158b570ddd0 100644 +--- a/drivers/edac/qcom_edac.c ++++ b/drivers/edac/qcom_edac.c +@@ -76,6 +76,8 @@ + #define DRP0_INTERRUPT_ENABLE BIT(6) + #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 + ++#define ECC_POLL_MSEC 5000 ++ + enum { + LLCC_DRAM_CE = 0, + LLCC_DRAM_UE, +@@ -285,8 +287,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) + return ret; + } + +-static irqreturn_t +-llcc_ecc_irq_handler(int irq, void *edev_ctl) ++static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) + { + struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; +@@ -332,6 +333,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) + return irq_rc; + } + ++static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) ++{ ++ llcc_ecc_irq_handler(0, edev_ctl); ++} ++ + static int qcom_llcc_edac_probe(struct platform_device *pdev) + { + struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; +@@ -359,29 +365,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) + edev_ctl->ctl_name = "llcc"; + edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + +- rc = edac_device_add_device(edev_ctl); +- if (rc) +- goto out_mem; +- +- platform_set_drvdata(pdev, edev_ctl); +- +- /* Request for ecc irq */ ++ /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; +- if (ecc_irq < 0) { +- rc = -ENODEV; +- goto out_dev; +- } +- rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, ++ if (ecc_irq > 0) { ++ /* Use interrupt mode if IRQ is available */ ++ rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); +- if (rc) +- goto out_dev; ++ if (!rc) { ++ edac_op_state = EDAC_OPSTATE_INT; ++ goto irq_done; ++ } ++ } + +- return rc; ++ /* Fall back to polling mode otherwise */ ++ edev_ctl->poll_msec = ECC_POLL_MSEC; ++ edev_ctl->edac_check = llcc_ecc_check; ++ edac_op_state = EDAC_OPSTATE_POLL; + +-out_dev: +- edac_device_del_device(edev_ctl->dev); +-out_mem: +- edac_device_free_ctl_info(edev_ctl); ++irq_done: ++ rc = edac_device_add_device(edev_ctl); ++ if (rc) { ++ edac_device_free_ctl_info(edev_ctl); ++ return rc; ++ } ++ ++ platform_set_drvdata(pdev, edev_ctl); + + return rc; + } +diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c +index 26efe12012a0d..e417bd285d9db 100644 +--- a/drivers/soc/qcom/llcc-qcom.c ++++ b/drivers/soc/qcom/llcc-qcom.c +@@ -1001,13 +1001,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) + goto err; + + drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); +- if (drv_data->ecc_irq >= 0) { +- llcc_edac = platform_device_register_data(&pdev->dev, +- "qcom_llcc_edac", -1, drv_data, +- sizeof(*drv_data)); +- if (IS_ERR(llcc_edac)) +- dev_err(dev, "Failed to register llcc edac driver\n"); +- } ++ ++ llcc_edac = platform_device_register_data(&pdev->dev, ++ "qcom_llcc_edac", -1, drv_data, ++ sizeof(*drv_data)); ++ if (IS_ERR(llcc_edac)) ++ dev_err(dev, "Failed to register llcc edac driver\n"); + + return 0; + err: +-- +2.39.2 + diff --git a/queue-6.3/series b/queue-6.3/series new file mode 100644 index 00000000000..6551c2b1312 --- /dev/null +++ b/queue-6.3/series @@ -0,0 +1,8 @@ +usb-dwc3-gadget-drop-dead-hibernation-code.patch +usb-dwc3-gadget-execute-gadget-stop-after-halting-th.patch +crypto-ccp-clear-psp-interrupt-status-register-befor.patch +mtd-spi-nor-add-a-rww-flag.patch +mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch +qcom-llcc-edac-support-polling-mode-for-ecc-handling.patch +soc-qcom-llcc-do-not-create-edac-platform-device-on-.patch +mtd-spi-nor-spansion-enable-jffs2-write-buffer-for-i.patch-29548 diff --git a/queue-6.3/soc-qcom-llcc-do-not-create-edac-platform-device-on-.patch b/queue-6.3/soc-qcom-llcc-do-not-create-edac-platform-device-on-.patch new file mode 100644 index 00000000000..bf8158756ea --- /dev/null +++ b/queue-6.3/soc-qcom-llcc-do-not-create-edac-platform-device-on-.patch @@ -0,0 +1,82 @@ +From e7427c424ac4a709326ae693feb9a6453a2ad483 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 14 Mar 2023 13:34:43 +0530 +Subject: soc: qcom: llcc: Do not create EDAC platform device on SDM845 + +From: Manivannan Sadhasivam + +[ Upstream commit cca94f1dd6d0a4c7e5c8190672f5747e3c00ddde ] + +The platforms based on SDM845 SoC locks the access to EDAC registers in the +bootloader. So probing the EDAC driver will result in a crash. Hence, +disable the creation of EDAC platform device on all SDM845 devices. + +The issue has been observed on Lenovo Yoga C630 and DB845c. + +While at it, also sort the members of `struct qcom_llcc_config` to avoid +any holes in-between. + +Cc: # 5.10 +Reported-by: Steev Klimaszewski +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230314080443.64635-15-manivannan.sadhasivam@linaro.org +Signed-off-by: Sasha Levin +--- + drivers/soc/qcom/llcc-qcom.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) + +diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c +index e417bd285d9db..d4d3eced52f35 100644 +--- a/drivers/soc/qcom/llcc-qcom.c ++++ b/drivers/soc/qcom/llcc-qcom.c +@@ -122,10 +122,11 @@ struct llcc_slice_config { + + struct qcom_llcc_config { + const struct llcc_slice_config *sct_data; +- int size; +- bool need_llcc_cfg; + const u32 *reg_offset; + const struct llcc_edac_reg_offset *edac_reg_offset; ++ int size; ++ bool need_llcc_cfg; ++ bool no_edac; + }; + + enum llcc_reg_offset { +@@ -454,6 +455,7 @@ static const struct qcom_llcc_config sdm845_cfg = { + .need_llcc_cfg = false, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, ++ .no_edac = true, + }; + + static const struct qcom_llcc_config sm6350_cfg = { +@@ -1002,11 +1004,19 @@ static int qcom_llcc_probe(struct platform_device *pdev) + + drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); + +- llcc_edac = platform_device_register_data(&pdev->dev, +- "qcom_llcc_edac", -1, drv_data, +- sizeof(*drv_data)); +- if (IS_ERR(llcc_edac)) +- dev_err(dev, "Failed to register llcc edac driver\n"); ++ /* ++ * On some platforms, the access to EDAC registers will be locked by ++ * the bootloader. So probing the EDAC driver will result in a crash. ++ * Hence, disable the creation of EDAC platform device for the ++ * problematic platforms. ++ */ ++ if (!cfg->no_edac) { ++ llcc_edac = platform_device_register_data(&pdev->dev, ++ "qcom_llcc_edac", -1, drv_data, ++ sizeof(*drv_data)); ++ if (IS_ERR(llcc_edac)) ++ dev_err(dev, "Failed to register llcc edac driver\n"); ++ } + + return 0; + err: +-- +2.39.2 + diff --git a/queue-6.3/usb-dwc3-gadget-drop-dead-hibernation-code.patch b/queue-6.3/usb-dwc3-gadget-drop-dead-hibernation-code.patch new file mode 100644 index 00000000000..c13cb45c36d --- /dev/null +++ b/queue-6.3/usb-dwc3-gadget-drop-dead-hibernation-code.patch @@ -0,0 +1,141 @@ +From eb5f8a713b6142949cdd64a132d2d9532469c2ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Apr 2023 09:25:17 +0200 +Subject: USB: dwc3: gadget: drop dead hibernation code + +From: Johan Hovold + +[ Upstream commit bdb19d01026a5cccfa437be8adcf2df472c5889e ] + +The hibernation code is broken and has never been enabled in mainline +and should thus be dropped. + +Remove the hibernation bits from the gadget code, which effectively +reverts commits e1dadd3b0f27 ("usb: dwc3: workaround: bogus hibernation +events") and 7b2a0368bbc9 ("usb: dwc3: gadget: set KEEP_CONNECT in case +of hibernation") except for the spurious interrupt warning. + +Acked-by: Thinh Nguyen +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20230404072524.19014-5-johan+linaro@kernel.org +Signed-off-by: Greg Kroah-Hartman +Stable-dep-of: 39674be56fba ("usb: dwc3: gadget: Execute gadget stop after halting the controller") +Signed-off-by: Sasha Levin +--- + drivers/usb/dwc3/gadget.c | 46 +++++---------------------------------- + 1 file changed, 6 insertions(+), 40 deletions(-) + +diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c +index 3faac3244c7db..a995e3f4df37f 100644 +--- a/drivers/usb/dwc3/gadget.c ++++ b/drivers/usb/dwc3/gadget.c +@@ -2478,7 +2478,7 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc) + dwc3_writel(dwc->regs, DWC3_DCFG, reg); + } + +-static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) ++static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) + { + u32 reg; + u32 timeout = 2000; +@@ -2497,17 +2497,11 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) + reg &= ~DWC3_DCTL_KEEP_CONNECT; + reg |= DWC3_DCTL_RUN_STOP; + +- if (dwc->has_hibernation) +- reg |= DWC3_DCTL_KEEP_CONNECT; +- + __dwc3_gadget_set_speed(dwc); + dwc->pullups_connected = true; + } else { + reg &= ~DWC3_DCTL_RUN_STOP; + +- if (dwc->has_hibernation && !suspend) +- reg &= ~DWC3_DCTL_KEEP_CONNECT; +- + dwc->pullups_connected = false; + } + +@@ -2589,7 +2583,7 @@ static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc) + * remaining event generated by the controller while polling for + * DSTS.DEVCTLHLT. + */ +- return dwc3_gadget_run_stop(dwc, false, false); ++ return dwc3_gadget_run_stop(dwc, false); + } + + static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) +@@ -2643,7 +2637,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) + + dwc3_event_buffers_setup(dwc); + __dwc3_gadget_start(dwc); +- ret = dwc3_gadget_run_stop(dwc, true, false); ++ ret = dwc3_gadget_run_stop(dwc, true); + } + + pm_runtime_put(dwc->dev); +@@ -4210,30 +4204,6 @@ static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, + dwc->link_state = next; + } + +-static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, +- unsigned int evtinfo) +-{ +- unsigned int is_ss = evtinfo & BIT(4); +- +- /* +- * WORKAROUND: DWC3 revision 2.20a with hibernation support +- * have a known issue which can cause USB CV TD.9.23 to fail +- * randomly. +- * +- * Because of this issue, core could generate bogus hibernation +- * events which SW needs to ignore. +- * +- * Refers to: +- * +- * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 +- * Device Fallback from SuperSpeed +- */ +- if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) +- return; +- +- /* enter hibernation here */ +-} +- + static void dwc3_gadget_interrupt(struct dwc3 *dwc, + const struct dwc3_event_devt *event) + { +@@ -4251,11 +4221,7 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc, + dwc3_gadget_wakeup_interrupt(dwc); + break; + case DWC3_DEVICE_EVENT_HIBER_REQ: +- if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, +- "unexpected hibernation event\n")) +- break; +- +- dwc3_gadget_hibernation_interrupt(dwc, event->event_info); ++ dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n"); + break; + case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: + dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); +@@ -4592,7 +4558,7 @@ int dwc3_gadget_suspend(struct dwc3 *dwc) + if (!dwc->gadget_driver) + return 0; + +- dwc3_gadget_run_stop(dwc, false, false); ++ dwc3_gadget_run_stop(dwc, false); + + spin_lock_irqsave(&dwc->lock, flags); + dwc3_disconnect_gadget(dwc); +@@ -4613,7 +4579,7 @@ int dwc3_gadget_resume(struct dwc3 *dwc) + if (ret < 0) + goto err0; + +- ret = dwc3_gadget_run_stop(dwc, true, false); ++ ret = dwc3_gadget_run_stop(dwc, true); + if (ret < 0) + goto err1; + +-- +2.39.2 + diff --git a/queue-6.3/usb-dwc3-gadget-execute-gadget-stop-after-halting-th.patch b/queue-6.3/usb-dwc3-gadget-execute-gadget-stop-after-halting-th.patch new file mode 100644 index 00000000000..87125ed53f6 --- /dev/null +++ b/queue-6.3/usb-dwc3-gadget-execute-gadget-stop-after-halting-th.patch @@ -0,0 +1,61 @@ +From 75ebcfaef941ee6a229a788e2cec4839c96f7ed1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 20 Apr 2023 14:27:58 -0700 +Subject: usb: dwc3: gadget: Execute gadget stop after halting the controller + +From: Wesley Cheng + +[ Upstream commit 39674be56fba1cd3a03bf4617f523a35f85fd2c1 ] + +Do not call gadget stop until the poll for controller halt is +completed. DEVTEN is cleared as part of gadget stop, so the intention to +allow ep0 events to continue while waiting for controller halt is not +happening. + +Fixes: c96683798e27 ("usb: dwc3: ep0: Don't prepare beyond Setup stage") +Cc: stable@vger.kernel.org +Acked-by: Thinh Nguyen +Signed-off-by: Wesley Cheng +Link: https://lore.kernel.org/r/20230420212759.29429-2-quic_wcheng@quicinc.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/dwc3/gadget.c | 15 +++++++++++++-- + 1 file changed, 13 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c +index a995e3f4df37f..e63700937ba8c 100644 +--- a/drivers/usb/dwc3/gadget.c ++++ b/drivers/usb/dwc3/gadget.c +@@ -2546,7 +2546,6 @@ static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc) + * bit. + */ + dwc3_stop_active_transfers(dwc); +- __dwc3_gadget_stop(dwc); + spin_unlock_irqrestore(&dwc->lock, flags); + + /* +@@ -2583,7 +2582,19 @@ static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc) + * remaining event generated by the controller while polling for + * DSTS.DEVCTLHLT. + */ +- return dwc3_gadget_run_stop(dwc, false); ++ ret = dwc3_gadget_run_stop(dwc, false); ++ ++ /* ++ * Stop the gadget after controller is halted, so that if needed, the ++ * events to update EP0 state can still occur while the run/stop ++ * routine polls for the halted state. DEVTEN is cleared as part of ++ * gadget stop. ++ */ ++ spin_lock_irqsave(&dwc->lock, flags); ++ __dwc3_gadget_stop(dwc); ++ spin_unlock_irqrestore(&dwc->lock, flags); ++ ++ return ret; + } + + static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) +-- +2.39.2 +