From: Greg Kroah-Hartman Date: Mon, 27 Aug 2012 18:09:32 +0000 (-0700) Subject: 3.5-stable patches X-Git-Tag: v3.5.4~57 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0d3a2c7c83ecfa008da8359e9b26489bf385a388;p=thirdparty%2Fkernel%2Fstable-queue.git 3.5-stable patches added patches: arm-imx6-spin-the-cpu-until-hardware-takes-it-down.patch arm-imx-build-i.mx6-functions-only-when-needed.patch arm-imx-build-pm-imx5-code-only-when-pm-is-enabled.patch arm-imx-select-cpu_freq_table-when-needed.patch --- diff --git a/queue-3.5/arm-imx-build-i.mx6-functions-only-when-needed.patch b/queue-3.5/arm-imx-build-i.mx6-functions-only-when-needed.patch new file mode 100644 index 00000000000..56af722f607 --- /dev/null +++ b/queue-3.5/arm-imx-build-i.mx6-functions-only-when-needed.patch @@ -0,0 +1,274 @@ +From 1fc593feaf8e440511f381f4cdff483b55bbf546 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 17 Aug 2012 00:16:08 +0000 +Subject: ARM: imx: build i.MX6 functions only when needed + +From: Arnd Bergmann + +commit 1fc593feaf8e440511f381f4cdff483b55bbf546 upstream. + +The head-v7.S contains a call to the generic cpu_suspend function, +which is only available when selected by the i.MX6 code. As +pointed out by Shawn Guo, i.MX5 does not actually use any +functions defined in head-v7.S. It is also needed only for +the i.MX6 power management code and for the SMP code, so +we can restrict building this file to situations in which +at least one of those two is present. + +Finally, other platforms with a similar file call it headsmp.S, +so we can rename it to the same for consistency. + +Without this patch, building imx5 standalone results in: + +arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': +arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume' + +Signed-off-by: Arnd Bergmann +Acked-by: Shawn Guo +Cc: Eric Miao +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-imx/Makefile | 7 +- + arch/arm/mach-imx/head-v7.S | 106 -------------------------------------------- + arch/arm/mach-imx/headsmp.S | 106 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 109 insertions(+), 110 deletions(-) + +--- a/arch/arm/mach-imx/Makefile ++++ b/arch/arm/mach-imx/Makefile +@@ -70,14 +70,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o + obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o + obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o + obj-$(CONFIG_HAVE_IMX_SRC) += src.o +-obj-$(CONFIG_CPU_V7) += head-v7.o +-AFLAGS_head-v7.o :=-Wa,-march=armv7-a +-obj-$(CONFIG_SMP) += platsmp.o ++AFLAGS_headsmp.o :=-Wa,-march=armv7-a ++obj-$(CONFIG_SMP) += headsmp.o platsmp.o + obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o + + ifeq ($(CONFIG_PM),y) +-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o ++obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o + endif + + # i.MX5 based machines +--- a/arch/arm/mach-imx/head-v7.S ++++ /dev/null +@@ -1,106 +0,0 @@ +-/* +- * Copyright 2011 Freescale Semiconductor, Inc. +- * Copyright 2011 Linaro Ltd. +- * +- * The code contained herein is licensed under the GNU General Public +- * License. You may obtain a copy of the GNU General Public License +- * Version 2 or later at the following locations: +- * +- * http://www.opensource.org/licenses/gpl-license.html +- * http://www.gnu.org/copyleft/gpl.html +- */ +- +-#include +-#include +-#include +-#include +- +- .section ".text.head", "ax" +- +-/* +- * The secondary kernel init calls v7_flush_dcache_all before it enables +- * the L1; however, the L1 comes out of reset in an undefined state, so +- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch +- * of cache lines with uninitialized data and uninitialized tags to get +- * written out to memory, which does really unpleasant things to the main +- * processor. We fix this by performing an invalidate, rather than a +- * clean + invalidate, before jumping into the kernel. +- * +- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs +- * to be called for both secondary cores startup and primary core resume +- * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. +- */ +-ENTRY(v7_invalidate_l1) +- mov r0, #0 +- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache +- mcr p15, 2, r0, c0, c0, 0 +- mrc p15, 1, r0, c0, c0, 0 +- +- ldr r1, =0x7fff +- and r2, r1, r0, lsr #13 +- +- ldr r1, =0x3ff +- +- and r3, r1, r0, lsr #3 @ NumWays - 1 +- add r2, r2, #1 @ NumSets +- +- and r0, r0, #0x7 +- add r0, r0, #4 @ SetShift +- +- clz r1, r3 @ WayShift +- add r4, r3, #1 @ NumWays +-1: sub r2, r2, #1 @ NumSets-- +- mov r3, r4 @ Temp = NumWays +-2: subs r3, r3, #1 @ Temp-- +- mov r5, r3, lsl r1 +- mov r6, r2, lsl r0 +- orr r5, r5, r6 @ Reg = (Temp< ++#include ++#include ++#include ++ ++ .section ".text.head", "ax" ++ ++/* ++ * The secondary kernel init calls v7_flush_dcache_all before it enables ++ * the L1; however, the L1 comes out of reset in an undefined state, so ++ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch ++ * of cache lines with uninitialized data and uninitialized tags to get ++ * written out to memory, which does really unpleasant things to the main ++ * processor. We fix this by performing an invalidate, rather than a ++ * clean + invalidate, before jumping into the kernel. ++ * ++ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs ++ * to be called for both secondary cores startup and primary core resume ++ * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. ++ */ ++ENTRY(v7_invalidate_l1) ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache ++ mcr p15, 2, r0, c0, c0, 0 ++ mrc p15, 1, r0, c0, c0, 0 ++ ++ ldr r1, =0x7fff ++ and r2, r1, r0, lsr #13 ++ ++ ldr r1, =0x3ff ++ ++ and r3, r1, r0, lsr #3 @ NumWays - 1 ++ add r2, r2, #1 @ NumSets ++ ++ and r0, r0, #0x7 ++ add r0, r0, #4 @ SetShift ++ ++ clz r1, r3 @ WayShift ++ add r4, r3, #1 @ NumWays ++1: sub r2, r2, #1 @ NumSets-- ++ mov r3, r4 @ Temp = NumWays ++2: subs r3, r3, #1 @ Temp-- ++ mov r5, r3, lsl r1 ++ mov r6, r2, lsl r0 ++ orr r5, r5, r6 @ Reg = (Temp< +Date: Wed, 15 Aug 2012 21:56:39 +0000 +Subject: ARM: imx: build pm-imx5 code only when PM is enabled + +From: Arnd Bergmann + +commit a28eecef8ac2671dce7d892165bf374eeaa04e15 upstream. + +This moves the imx5 pm code out of the list of unconditionally +compiled files for imx5, mirroring what we already do for imx6 +and how it was done before the code was move from mach-mx5 to +mach-imx in v3.3. + +Without this patch, building with CONFIG_PM disabled results in: + +arch/arm/mach-imx/pm-imx5.c:202:116: error: redefinition of 'imx51_pm_init' +arch/arm/mach-imx/include/mach-imx/common.h:154:91: note: previous definition of 'imx51_pm_init' was here +arch/arm/mach-imx/pm-imx5.c:209:116: error: redefinition of 'imx53_pm_init' +arch/arm/mach-imx/include/mach-imx/common.h:155:91: note: previous definition of 'imx53_pm_init' was here + +Signed-off-by: Arnd Bergmann +Acked-by: Shawn Guo +Cc: Sascha Hauer +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-imx/Makefile | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-imx/Makefile ++++ b/arch/arm/mach-imx/Makefile +@@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o m + obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o + obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o + +-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o ++imx5-pm-$(CONFIG_PM) += pm-imx5.o ++obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o + + obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ + clk-pfd.o clk-busy.o diff --git a/queue-3.5/arm-imx-select-cpu_freq_table-when-needed.patch b/queue-3.5/arm-imx-select-cpu_freq_table-when-needed.patch new file mode 100644 index 00000000000..5945638a5f8 --- /dev/null +++ b/queue-3.5/arm-imx-select-cpu_freq_table-when-needed.patch @@ -0,0 +1,46 @@ +From f637c4c9405e21f44cf0045eaf77eddd3a79ca5a Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Thu, 16 Aug 2012 10:40:40 +0000 +Subject: ARM: imx: select CPU_FREQ_TABLE when needed + +From: Arnd Bergmann + +commit f637c4c9405e21f44cf0045eaf77eddd3a79ca5a upstream. + +The i.MX cpufreq implementation uses the CPU_FREQ_TABLE helpers, +so it needs to select that code to be built. This problem has +apparently existed since the i.MX cpufreq code was first merged +in v2.6.37. + +Building IMX without CPU_FREQ_TABLE results in: + +arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_exit': +arch/arm/plat-mxc/cpufreq.c:173: undefined reference to `cpufreq_frequency_table_put_attr' +arch/arm/plat-mxc/built-in.o: In function `mxc_set_target': +arch/arm/plat-mxc/cpufreq.c:84: undefined reference to `cpufreq_frequency_table_target' +arch/arm/plat-mxc/built-in.o: In function `mxc_verify_speed': +arch/arm/plat-mxc/cpufreq.c:65: undefined reference to `cpufreq_frequency_table_verify' +arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_init': +arch/arm/plat-mxc/cpufreq.c:154: undefined reference to `cpufreq_frequency_table_cpuinfo' +arch/arm/plat-mxc/cpufreq.c:162: undefined reference to `cpufreq_frequency_table_get_attr' + +Signed-off-by: Arnd Bergmann +Acked-by: Shawn Guo +Cc: Sascha Hauer +Cc: Yong Shen +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -2083,6 +2083,7 @@ source "drivers/cpufreq/Kconfig" + config CPU_FREQ_IMX + tristate "CPUfreq driver for i.MX CPUs" + depends on ARCH_MXC && CPU_FREQ ++ select CPU_FREQ_TABLE + help + This enables the CPUfreq driver for i.MX CPUs. + diff --git a/queue-3.5/arm-imx6-spin-the-cpu-until-hardware-takes-it-down.patch b/queue-3.5/arm-imx6-spin-the-cpu-until-hardware-takes-it-down.patch new file mode 100644 index 00000000000..856c372a341 --- /dev/null +++ b/queue-3.5/arm-imx6-spin-the-cpu-until-hardware-takes-it-down.patch @@ -0,0 +1,68 @@ +From c944b0b9354ea06ffb0c8a7178949f1185f9f499 Mon Sep 17 00:00:00 2001 +From: Shawn Guo +Date: Sat, 18 Aug 2012 14:27:32 +0800 +Subject: ARM: imx6: spin the cpu until hardware takes it down + +From: Shawn Guo + +commit c944b0b9354ea06ffb0c8a7178949f1185f9f499 upstream. + +Though commit 602bf40 (ARM: imx6: exit coherency when shutting down +a cpu) improves the stability of imx6q cpu hotplug a lot, there are +still hangs seen with a more stressful hotplug testing. + +It's expected that once imx_enable_cpu(cpu, false) is called, the cpu +will be taken down by hardware immediately, and the code after that +will not get any chance to execute. However, this is not always the +case from the testing. The cpu could possibly be alive for a few +cycles before hardware actually takes it down. So rather than letting +cpu execute some code that could cause a hang in these cycles, let's +make the cpu spin there and wait for hardware to take it down. + +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-imx/hotplug.c | 23 +++-------------------- + 1 file changed, 3 insertions(+), 20 deletions(-) + +--- a/arch/arm/mach-imx/hotplug.c ++++ b/arch/arm/mach-imx/hotplug.c +@@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(vo + : "cc"); + } + +-static inline void cpu_leave_lowpower(void) +-{ +- unsigned int v; +- +- asm volatile( +- "mrc p15, 0, %0, c1, c0, 0\n" +- " orr %0, %0, %1\n" +- " mcr p15, 0, %0, c1, c0, 0\n" +- " mrc p15, 0, %0, c1, c0, 1\n" +- " orr %0, %0, %2\n" +- " mcr p15, 0, %0, c1, c0, 1\n" +- : "=&r" (v) +- : "Ir" (CR_C), "Ir" (0x40) +- : "cc"); +-} +- + /* + * platform-specific code to shutdown a CPU + * +@@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu) + { + cpu_enter_lowpower(); + imx_enable_cpu(cpu, false); +- cpu_do_idle(); +- cpu_leave_lowpower(); + +- /* We should never return from idle */ +- panic("cpu %d unexpectedly exit from shutdown\n", cpu); ++ /* spin here until hardware takes it down */ ++ while (1) ++ ; + } + + int platform_cpu_disable(unsigned int cpu) diff --git a/queue-3.5/series b/queue-3.5/series index 5f31c440cd0..24855c54e2a 100644 --- a/queue-3.5/series +++ b/queue-3.5/series @@ -10,3 +10,7 @@ arm-s3c24xx-add-missing-dmach_dt_prop.patch arm-s3c24xx-fix-s3c2410_dma_enqueue-parameters.patch xen-p2m-reuse-existing-p2m-leafs-if-they-are-filled-with-1-1-pfns-or-invalid.patch xen-setup-fix-one-off-error-when-adding-for-balloon-pfns-to-the-p2m.patch +arm-imx6-spin-the-cpu-until-hardware-takes-it-down.patch +arm-imx-build-pm-imx5-code-only-when-pm-is-enabled.patch +arm-imx-select-cpu_freq_table-when-needed.patch +arm-imx-build-i.mx6-functions-only-when-needed.patch