From: Tao Su Date: Thu, 31 Oct 2024 08:52:32 +0000 (+0800) Subject: target/i386: Add AVX512 state when AVX10 is supported X-Git-Tag: v9.2.0-rc0~27^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0d7475be3b402c25d74c5a4573cbeb733c8f3559;p=thirdparty%2Fqemu.git target/i386: Add AVX512 state when AVX10 is supported AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register are identical to AVX512 state regardless of the supported vector lengths. Given that some E-cores will support AVX10 but not support AVX512, add AVX512 state components to guest when AVX10 is enabled. Based on a patch by Tao Su Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Xuelian Guo Signed-off-by: Tao Su Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini --- diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d056285a034..7666a50bf06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7156,7 +7156,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) return false; } - return (env->features[esa->feature] & esa->bits); + if (env->features[esa->feature] & esa->bits) { + return true; + } + if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F + && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + return true; + } + + return false; } static void x86_cpu_reset_hold(Object *obj, ResetType type)