From: sje <sje@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon, 18 Nov 2013 19:20:12 +0000 (+0000)
Subject: 2013-11-18  Andrew Pinski <apinski@cavium.com>
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=0e4d8867624b6e0afb98061c08aff59b54530432;p=thirdparty%2Fgcc.git

2013-11-18  Andrew Pinski <apinski@cavium.com>
	    Steve Ellcey  <sellcey@mips.com>

	PR target/56552
	* config/mips/mips.md (*mov<GPR:mode>_on_<MOVECC:mode>): Remove
	type restriction from equality_operator on conditonal move.
	(*mov<SCALARF:mode>_on_<MOVECC:mode>): Ditto.
	(*mov<GPR:mode>_on_<GPR2:mode>_ne): New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204979 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d61b4946aa84..3e88c0421ecd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2013-11-18  Andrew Pinski <apinski@cavium.com>
+	    Steve Ellcey  <sellcey@mips.com>
+
+	PR target/56552
+	* config/mips/mips.md (*mov<GPR:mode>_on_<MOVECC:mode>): Remove
+	type restriction from equality_operator on conditonal move.
+	(*mov<SCALARF:mode>_on_<MOVECC:mode>): Ditto.
+	(*mov<GPR:mode>_on_<GPR2:mode>_ne): New.
+
 2013-11-18  Jeff Law  <law@redhat.com>
 
 	* tree-ssa-threadupdate.c: Fix file block comment.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 3554beb30337..6991f203df44 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -6776,7 +6776,7 @@
 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
   [(set (match_operand:GPR 0 "register_operand" "=d,d")
 	(if_then_else:GPR
-	 (match_operator:MOVECC 4 "equality_operator"
+	 (match_operator 4 "equality_operator"
 		[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
@@ -6788,10 +6788,23 @@
   [(set_attr "type" "condmove")
    (set_attr "mode" "<GPR:MODE>")])
 
+(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
+  [(set (match_operand:GPR 0 "register_operand" "=d,d")
+       (if_then_else:GPR
+        (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
+        (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
+        (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
+  "ISA_HAS_CONDMOVE"
+  "@
+    movn\t%0,%z2,%1
+    movz\t%0,%z3,%1"
+  [(set_attr "type" "condmove")
+   (set_attr "mode" "<GPR:MODE>")])
+
 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
   [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
 	(if_then_else:SCALARF
-	 (match_operator:MOVECC 4 "equality_operator"
+	 (match_operator 4 "equality_operator"
 		[(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
 		 (const_int 0)])
 	 (match_operand:SCALARF 2 "register_operand" "f,0")