From: Michal Simek Date: Fri, 28 Jun 2019 08:51:33 +0000 (+0200) Subject: arm64: versal: Switch all versal platform to firmware clocks X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=100650c71913d23a1e531af2c5285b51deb33821;p=thirdparty%2Fu-boot.git arm64: versal: Switch all versal platform to firmware clocks Do not use fixed clock and move to firmware managed clocks for all current platforms. versal-fixed.dtsi can be removed at this point. Signed-off-by: Michal Simek --- diff --git a/arch/arm/dts/versal-clk.dtsi b/arch/arm/dts/versal-clk.dtsi new file mode 100644 index 00000000000..8363a089b74 --- /dev/null +++ b/arch/arm/dts/versal-clk.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal with PM + * + * (C) Copyright 2017 - 2019, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include + +/ { + alt_ref_clk: alt_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + pl_alt_ref_clk: pl_alt_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + ref_clk: ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + firmware { + versal_firmware: versal-firmware { + compatible = "xlnx,versal-firmware-wip"; + u-boot,dm-pre-reloc; + method = "smc"; + #power-domain-cells = <1>; + + versal_clk: clock-controller { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,versal-clk"; + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; + }; + + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + interrupt-parent = <&gic>; + interrupts = <0 30 4>; + mboxes = <&ipi_mailbox_pmu1 0>, + <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; + }; + }; + }; + + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 30 4>; + xlnx,ipi-id = <2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@ff3f0440 { + reg = <0 0xff3f0440 0 0x20>, + <0 0xff3f0460 0 0x20>, + <0 0xff3f0280 0 0x20>, + <0 0xff3f02a0 0 0x20>; + reg-names = "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; + }; + }; +}; + +&can0 { + clocks = <&versal_clk CAN0_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_CAN_FD_0>; +}; + +&can1 { + clocks = <&versal_clk CAN1_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_CAN_FD_1>; +}; + +&gem0 { + clocks = <&versal_clk LPD_LSBUS>, + <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, + <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; + power-domains = <&versal_firmware PD_GEM_0>; +}; + +&gem1 { + clocks = <&versal_clk LPD_LSBUS>, + <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, + <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; + power-domains = <&versal_firmware PD_GEM_1>; +}; + +&gpio { + clocks = <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_GPIO>; +}; + +&i2c0 { + clocks = <&versal_clk I2C0_REF>; + power-domains = <&versal_firmware PD_I2C_0>; +}; + +&i2c1 { + clocks = <&versal_clk I2C1_REF>; + power-domains = <&versal_firmware PD_I2C_1>; +}; + +&lpd_dma_chan0 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_0>; +}; + +&lpd_dma_chan1 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_1>; +}; + +&lpd_dma_chan2 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_2>; +}; + +&lpd_dma_chan3 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_3>; +}; + +&lpd_dma_chan4 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_4>; +}; + +&lpd_dma_chan5 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_5>; +}; + +&lpd_dma_chan6 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_6>; +}; + +&lpd_dma_chan7 { + clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_ADMA_7>; +}; + +&qspi { + clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_QSPI>; +}; + +&ospi { + clocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>; +}; + +&rtc { + power-domains = <&versal_firmware PD_RTC>; +}; + +&serial0 { + clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_UART_0>; +}; + +&serial1 { + clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_UART_1>; +}; + +&sdhci0 { + clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_SDIO_0>; +}; + +&sdhci1 { + clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_SDIO_1>; +}; + +&spi0 { + clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_SPI_0>; +}; + +&spi1 { + clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; + power-domains = <&versal_firmware PD_SPI_1>; +}; + +&usb0 { + clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; + power-domains = <&versal_firmware PD_USB_0>; +}; + +&watchdog { + clocks = <&versal_clk LPD_LSBUS>; +}; diff --git a/arch/arm/dts/versal-fixed.dtsi b/arch/arm/dts/versal-fixed.dtsi deleted file mode 100644 index a6b7cda9a52..00000000000 --- a/arch/arm/dts/versal-fixed.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Xilinx Versal fixed clock default configuration - * - * (C) Copyright 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/ { - clk60: clk60 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <60000000>; - u-boot,dm-pre-reloc; - }; - - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - u-boot,dm-pre-reloc; - }; - - clk125: clk125 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk150: clk150 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <150000000>; - }; - - clk160: clk160 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <160000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; -}; - -&can0 { - clocks = <&clk160 &clk100>; -}; - -&can1 { - clocks = <&clk160 &clk100>; -}; - -&lpd_dma_chan0 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan1 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan2 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan3 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan4 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan5 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan6 { - clocks = <&clk100 &clk100>; -}; - -&lpd_dma_chan7 { - clocks = <&clk100 &clk100>; -}; - -&gpio { - clocks = <&clk100>; -}; - -&gem0 { - clocks = <&clk100 &clk125 &clk125 &clk125 &clk250>; -}; - -&gem1 { - clocks = <&clk100 &clk125 &clk125 &clk125 &clk250>; -}; - -&qspi { - clocks = <&clk300 &clk100>; -}; - -&ospi { - clocks = <&clk200 &clk100>; -}; - -&i2c0 { - clocks = <&clk100>; -}; - -&i2c1 { - clocks = <&clk100>; -}; - -&sdhci0 { - clocks = <&clk200 &clk200>; -}; - -&sdhci1 { - clocks = <&clk200 &clk200>; -}; - -&serial0 { - clocks = <&clk100 &clk100>; -}; - -&serial1 { - clocks = <&clk100 &clk100>; -}; - -&spi0 { - clocks = <&clk200 &clk200>; -}; - -&spi1 { - clocks = <&clk200 &clk200>; -}; - -&usb0 { - clocks = <&clk60 &clk60>; -}; - -&watchdog { - clocks = <&clk100>; -}; diff --git a/arch/arm/dts/versal-vc-d-d1760-01-revA.dts b/arch/arm/dts/versal-vc-d-d1760-01-revA.dts index a1f09ab2d38..1f787f72bb2 100644 --- a/arch/arm/dts/versal-vc-d-d1760-01-revA.dts +++ b/arch/arm/dts/versal-vc-d-d1760-01-revA.dts @@ -8,7 +8,7 @@ */ #include "versal.dtsi" -#include "versal-fixed.dtsi" +#include "versal-clk.dtsi" / { compatible = "xlnx,versal-vc-d-d1760-01-revA", diff --git a/arch/arm/dts/versal-vc-e-a2197-00-revA.dts b/arch/arm/dts/versal-vc-e-a2197-00-revA.dts index 922fbffa54b..720de2f676c 100644 --- a/arch/arm/dts/versal-vc-e-a2197-00-revA.dts +++ b/arch/arm/dts/versal-vc-e-a2197-00-revA.dts @@ -8,7 +8,7 @@ */ #include "versal.dtsi" -#include "versal-fixed.dtsi" +#include "versal-clk.dtsi" / { compatible = "xlnx,versal-vc-e-a2197-00-revA", diff --git a/arch/arm/dts/versal-vc-p-a2197-00-revA.dts b/arch/arm/dts/versal-vc-p-a2197-00-revA.dts index 54c38bb624e..d96f2baf757 100644 --- a/arch/arm/dts/versal-vc-p-a2197-00-revA.dts +++ b/arch/arm/dts/versal-vc-p-a2197-00-revA.dts @@ -8,7 +8,7 @@ */ #include "versal.dtsi" -#include "versal-fixed.dtsi" +#include "versal-clk.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA",