From: Anup Patel Date: Wed, 11 Nov 2020 09:47:25 +0000 (+0530) Subject: hw/riscv: sifive_u: Add UART1 DT node in the generated DTB X-Git-Tag: v6.0.0-rc0~174^2~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=10b43754cf299af85bdb1996594ddd54bc517094;p=thirdparty%2Fqemu.git hw/riscv: sifive_u: Add UART1 DT node in the generated DTB The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20201111094725.3768755-1-anup.patel@wdc.com Signed-off-by: Alistair Francis --- diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e7f6dc5fb3d..a629416785c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -385,6 +385,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); + nodename = g_strdup_printf("/soc/serial@%lx", + (long)memmap[SIFIVE_U_DEV_UART1].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_UART1].base, + 0x0, memmap[SIFIVE_U_DEV_UART1].size); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); + + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); + g_free(nodename); + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_DEV_UART0].base); qemu_fdt_add_subnode(fdt, nodename);