From: Kito Cheng Date: Tue, 29 Apr 2025 03:40:15 +0000 (+0800) Subject: RISC-V: Mark fgt.*/fge.* as instruction alias X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=10ec3d5de0ee75ad56029bfa6b5d3be99f4eac3c;p=thirdparty%2Fbinutils-gdb.git RISC-V: Mark fgt.*/fge.* as instruction alias They are instruction alias, but not mark correctly, and seems like we don't have a good way to verify that since the disassembler doesn't disassemble instruction into alias. [1] https://github.com/riscv-non-isa/riscv-asm-manual/pull/124 --- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index e07f72b89f2..6f49fdbaa7c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -907,8 +907,8 @@ const struct riscv_opcode riscv_opcodes[] = {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, {"fle.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, -{"fgt.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, -{"fge.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, +{"fgt.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, INSN_ALIAS }, +{"fge.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, INSN_ALIAS }, {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, {"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, @@ -990,8 +990,8 @@ const struct riscv_opcode riscv_opcodes[] = {"feq.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, {"flt.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, {"fle.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, -{"fgt.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, -{"fge.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{"fgt.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_ALIAS }, +{"fge.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_ALIAS }, {"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 }, {"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, {"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 }, @@ -1049,8 +1049,8 @@ const struct riscv_opcode riscv_opcodes[] = {"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, {"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, {"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS }, +{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, {"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, @@ -1109,8 +1109,8 @@ const struct riscv_opcode riscv_opcodes[] = {"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, {"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, {"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, +{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS }, +{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS }, {"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, {"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },