From: Stephen Boyd <sboyd@kernel.org>
Date: Mon, 6 Oct 2025 18:00:55 +0000 (-0500)
Subject: Merge branch 'clk-determine-rate' into clk-next
X-Git-Tag: v6.18-rc1~50^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=112104e2b72c5c7ba1590e3a5614b2ff76474f14;p=thirdparty%2Fkernel%2Fstable.git

Merge branch 'clk-determine-rate' into clk-next

* clk-determine-rate: (120 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: scmi: migrate round_rate() to determine_rate()
  clk: ti: fapll: convert from round_rate() to determine_rate()
  clk: ti: dra7-atl: convert from round_rate() to determine_rate()
  clk: ti: divider: convert from round_rate() to determine_rate()
  clk: ti: composite: convert from round_rate() to determine_rate()
  clk: ti: dpll: convert from round_rate() to determine_rate()
  clk: ti: dpll: change error return from ~0 to -EINVAL
  clk: ti: dpll: remove round_rate() in favor of determine_rate()
  clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
  clk: tegra: super: convert from round_rate() to determine_rate()
  clk: tegra: pll: convert from round_rate() to determine_rate()
  clk: tegra: periph: divider: convert from round_rate() to determine_rate()
  clk: tegra: divider: convert from round_rate() to determine_rate()
  clk: tegra: audio-sync: convert from round_rate() to determine_rate()
  clk: fixed-factor: drop round_rate() clk ops
  clk: divider: remove round_rate() in favor of determine_rate()
  clk: visconti: pll: convert from round_rate() to determine_rate()
  clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
  ...
---

112104e2b72c5c7ba1590e3a5614b2ff76474f14
diff --cc drivers/clk/mediatek/clk-pll.c
index d717a120793b2,139d3bfcf45f9..cd2b6ce551c6b
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@@ -309,16 -286,6 +312,16 @@@ const struct clk_ops mtk_pll_ops = 
  	.set_rate	= mtk_pll_set_rate,
  };
  
 +const struct clk_ops mtk_pll_fenc_clr_set_ops = {
 +	.is_prepared	= mtk_pll_fenc_is_prepared,
 +	.prepare	= mtk_pll_prepare_setclr,
 +	.unprepare	= mtk_pll_unprepare_setclr,
 +	.recalc_rate	= mtk_pll_recalc_rate,
- 	.round_rate	= mtk_pll_round_rate,
++	.determine_rate	= mtk_pll_determine_rate,
 +	.set_rate	= mtk_pll_set_rate,
 +};
 +EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops);
 +
  struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
  					const struct mtk_pll_data *data,
  					void __iomem *base,