From: Richard Henderson Date: Tue, 10 Oct 2023 21:44:32 +0000 (-0700) Subject: target/sparc: Move gen_fop_FF insns to decodetree X-Git-Tag: v8.2.0-rc0~49^2~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=119cb94f69e2180f1a8685b53a0659f195bdd90c;p=thirdparty%2Fqemu.git target/sparc: Move gen_fop_FF insns to decodetree Move FSQRTs, FiTOs, FsTOi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index bc449023ddf..85464285b7b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -245,6 +245,9 @@ FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 +FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 +FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 197c0bea540..13932e087d0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1654,20 +1654,6 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } -static void gen_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) -{ - TCGv_i32 dst, src; - - src = gen_load_fpr_F(dc, rs); - dst = gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) { @@ -4806,6 +4792,27 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) +static bool do_env_ff(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + tmp = gen_load_fpr_F(dc, a->rs); + func(tmp, tcg_env, tmp); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, tmp); + return advance_pc(dc); +} + +TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts) +TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos) +TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi) + static bool do_dd(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_i64)) { @@ -4967,10 +4974,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x2: /* V9 fmovd */ case 0x6: /* V9 fnegd */ case 0xa: /* V9 fabsd */ - g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ - gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); - break; + case 0xc4: /* fitos */ + case 0xd1: /* fstoi */ + g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; @@ -5026,9 +5033,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); break; - case 0xc4: /* fitos */ - gen_fop_FF(dc, rd, rs2, gen_helper_fitos); - break; case 0xc6: /* fdtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); break; @@ -5058,9 +5062,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd1: /* fstoi */ - gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); - break; case 0xd2: /* fdtoi */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); break;