From: Greg Kroah-Hartman Date: Fri, 16 Mar 2012 21:00:45 +0000 (-0700) Subject: 3.2-stable patches X-Git-Tag: v3.0.25~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1246101a0054931f9377eb599ed1510ade600b74;p=thirdparty%2Fkernel%2Fstable-queue.git 3.2-stable patches added patches: hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch --- diff --git a/queue-3.2/hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch b/queue-3.2/hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch new file mode 100644 index 00000000000..8e914b75982 --- /dev/null +++ b/queue-3.2/hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch @@ -0,0 +1,67 @@ +From fecfb64422d91a9621a3f96ab75c3a5f13e80b58 Mon Sep 17 00:00:00 2001 +From: Guenter Roeck +Date: Tue, 13 Mar 2012 09:05:14 -0700 +Subject: hwmon: (zl6100) Enable interval between chip accesses for all chips + +From: Guenter Roeck + +commit fecfb64422d91a9621a3f96ab75c3a5f13e80b58 upstream. + +Intersil reports that all chips supported by the zl6100 driver require +an interval between chip accesses, even ZL2004 and ZL6105 which were thought +to be safe. + +Reported-by: Vivek Gani +Signed-off-by: Guenter Roeck +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/hwmon/zl6100 | 14 ++++++-------- + drivers/hwmon/pmbus/zl6100.c | 11 +++-------- + 2 files changed, 9 insertions(+), 16 deletions(-) + +--- a/Documentation/hwmon/zl6100 ++++ b/Documentation/hwmon/zl6100 +@@ -73,14 +73,12 @@ Module parameters + delay + ----- + +-Some Intersil/Zilker Labs DC-DC controllers require a minimum interval between +-I2C bus accesses. According to Intersil, the minimum interval is 2 ms, though +-1 ms appears to be sufficient and has not caused any problems in testing. +-The problem is known to affect ZL6100, ZL2105, and ZL2008. It is known not to +-affect ZL2004 and ZL6105. The driver automatically sets the interval to 1 ms +-except for ZL2004 and ZL6105. To enable manual override, the driver provides a +-writeable module parameter, 'delay', which can be used to set the interval to +-a value between 0 and 65,535 microseconds. ++Intersil/Zilker Labs DC-DC controllers require a minimum interval between I2C ++bus accesses. According to Intersil, the minimum interval is 2 ms, though 1 ms ++appears to be sufficient and has not caused any problems in testing. The problem ++is known to affect all currently supported chips. For manual override, the ++driver provides a writeable module parameter, 'delay', which can be used to set ++the interval to a value between 0 and 65,535 microseconds. + + + Sysfs entries +--- a/drivers/hwmon/pmbus/zl6100.c ++++ b/drivers/hwmon/pmbus/zl6100.c +@@ -178,16 +178,11 @@ static int zl6100_probe(struct i2c_clien + data->id = mid->driver_data; + + /* +- * ZL2008, ZL2105, and ZL6100 are known to require a wait time +- * between I2C accesses. ZL2004 and ZL6105 are known to be safe. +- * +- * Only clear the wait time for chips known to be safe. The wait time +- * can be cleared later for additional chips if tests show that it +- * is not needed (in other words, better be safe than sorry). ++ * According to information from the chip vendor, all currently ++ * supported chips are known to require a wait time between I2C ++ * accesses. + */ + data->delay = delay; +- if (data->id == zl2004 || data->id == zl6105) +- data->delay = 0; + + /* + * Since there was a direct I2C device access above, wait before diff --git a/queue-3.2/series b/queue-3.2/series index b96fe7536f2..020eef25a38 100644 --- a/queue-3.2/series +++ b/queue-3.2/series @@ -38,3 +38,4 @@ rapidio-tsi721-fix-bug-in-register-offset-definitions.patch i2c-algo-bit-fix-spurious-scl-timeouts-under-heavy-load.patch iscsi-target-fix-reservation-conflict-ebusy-response-handling-bug.patch target-fix-compatible-reservation-handling-crh-1-with-legacy-reserve-release.patch +hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch