From: Alistair Francis <alistair.francis@wdc.com>
Date: Fri, 23 Aug 2019 15:21:22 +0000 (-0700)
Subject: target/riscv: Fix mstatus dirty mask
X-Git-Tag: v4.2.0-rc0~96^2~2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=14115b91ddb106b3e05c74c26a056b253ca666ea;p=thirdparty%2Fqemu.git

target/riscv: Fix mstatus dirty mask

This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.

Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2789215b5e2..f767ad24be3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
              * RV32: MPV and MTL are not in mstatus. The current plan is to
              * add them to mstatush. For now, we just don't support it.
              */
-            mask |= MSTATUS_MPP | MSTATUS_MPV;
+            mask |= MSTATUS_MTL | MSTATUS_MPV;
 #endif
     }