From: Anton Blanchard Date: Tue, 4 Jun 2019 19:01:11 +0000 (+0100) Subject: target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p X-Git-Tag: v4.0.1~80 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=14c9bbab092e497ed737f320e2b6da4a2c888d90;p=thirdparty%2Fqemu.git target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p We were using set_cpu_vsr*() when we should have used get_cpu_vsr*(). Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard Message-Id: <20190509104912.6b754dff@kryten> Reviewed-by: Mark Cave-Ayland Signed-off-by: David Gibson (upstream commit 77bd8937c03dd55e57cc257951ad07c185303c3e) Acked-by: David Gibson Signed-off-by: Michael Roth --- diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 489b2436e49..1b483fc27ea 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -858,8 +858,8 @@ static void glue(gen_, name)(DisasContext * ctx) \ xbh = tcg_temp_new_i64(); \ xbl = tcg_temp_new_i64(); \ sgm = tcg_temp_new_i64(); \ - set_cpu_vsrh(xB(ctx->opcode), xbh); \ - set_cpu_vsrl(xB(ctx->opcode), xbl); \ + get_cpu_vsrh(xbh, xB(ctx->opcode)); \ + get_cpu_vsrl(xbl, xB(ctx->opcode)); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \