From: Alistair Francis Date: Mon, 8 Jan 2024 00:13:27 +0000 (+1000) Subject: target/riscv: Don't adjust vscause for exceptions X-Git-Tag: v9.0.0-rc0~114^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1525d8aa3a56610e1c72f5dd305ec86ebad41769;p=thirdparty%2Fqemu.git target/riscv: Don't adjust vscause for exceptions We have been incorrectly adjusting both the interrupt and exception cause when using the hypervisor extension and trapping to VS-mode. This patch changes the conditional to ensure we only adjust the cause for interrupts and not exceptions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1708 Signed-off-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20240108001328.280222-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 99d1275729f..c7cc7eb423a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1749,8 +1749,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) * See if we need to adjust cause. Yes if its VS mode interrupt * no if hypervisor has delegated one of hs mode's interrupt */ - if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || - cause == IRQ_VS_EXT) { + if (async && (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT)) { cause = cause - 1; } write_gva = false;