From: Beniamin Sandu <beniaminsandu@gmail.com>
Date: Wed, 15 May 2024 18:12:49 +0000 (+0100)
Subject: arm64: dts: socfpga: stratix10: add L2 cache info
X-Git-Tag: v6.11-rc1~188^2~38^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1536dc8edc653e0e4a333035a73ff146d0517749;p=thirdparty%2Flinux.git

arm64: dts: socfpga: stratix10: add L2 cache info

This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index cbbc53c479218..0def0b0daaf73 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -34,6 +34,7 @@
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&l2_shared>;
 			reg = <0x0>;
 		};
 
@@ -41,6 +42,7 @@
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&l2_shared>;
 			reg = <0x1>;
 		};
 
@@ -48,6 +50,7 @@
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&l2_shared>;
 			reg = <0x2>;
 		};
 
@@ -55,8 +58,15 @@
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&l2_shared>;
 			reg = <0x3>;
 		};
+
+		l2_shared: cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
 	};
 
 	firmware {