From: Greg Kroah-Hartman Date: Wed, 15 Sep 2021 14:39:57 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v5.14.5~29 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=15695f64c29cffe677b07f7e99d57b00adf3d87f;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: arm-9105-1-atags_to_fdt-don-t-warn-about-stack-size.patch arm-9109-1-oabi-compat-add-epoll_pwait-handler.patch libata-add-ata_horkage_no_ncq_trim-for-samsung-860-and-870-ssds.patch pci-aardvark-fix-checking-for-pio-status.patch pci-aardvark-fix-masking-and-unmasking-legacy-intx-interrupts.patch pci-aardvark-increase-polling-delay-to-1.5s-while-waiting-for-pio-response.patch pci-portdrv-enable-bandwidth-notification-only-if-port-supports-it.patch pci-restrict-asmedia-asm1062-sata-max-payload-size-supported.patch pci-return-0-data-on-pciconfig_read-cap_sys_admin-failure.patch pci-xilinx-nwl-enable-the-clock-through-ccf.patch --- diff --git a/queue-5.4/arm-9105-1-atags_to_fdt-don-t-warn-about-stack-size.patch b/queue-5.4/arm-9105-1-atags_to_fdt-don-t-warn-about-stack-size.patch new file mode 100644 index 00000000000..c20c8b3077d --- /dev/null +++ b/queue-5.4/arm-9105-1-atags_to_fdt-don-t-warn-about-stack-size.patch @@ -0,0 +1,46 @@ +From b30d0289de72c62516df03fdad8d53f552c69839 Mon Sep 17 00:00:00 2001 +From: David Heidelberg +Date: Mon, 9 Aug 2021 19:07:30 +0100 +Subject: ARM: 9105/1: atags_to_fdt: don't warn about stack size + +From: David Heidelberg + +commit b30d0289de72c62516df03fdad8d53f552c69839 upstream. + +The merge_fdt_bootargs() function by definition consumes more than 1024 +bytes of stack because it has a 1024 byte command line on the stack, +meaning that we always get a warning when building this file: + +arch/arm/boot/compressed/atags_to_fdt.c: In function 'merge_fdt_bootargs': +arch/arm/boot/compressed/atags_to_fdt.c:98:1: warning: the frame size of 1032 bytes is larger than 1024 bytes [-Wframe-larger-than=] + +However, as this is the decompressor and we know that it has a very shallow +call chain, and we do not actually risk overflowing the kernel stack +at runtime here. + +This just shuts up the warning by disabling the warning flag for this +file. + +Tested on Nexus 7 2012 builds. + +Acked-by: Nicolas Pitre +Signed-off-by: David Heidelberg +Signed-off-by: Arnd Bergmann +Cc: +Signed-off-by: Russell King (Oracle) +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/boot/compressed/Makefile | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -90,6 +90,8 @@ $(addprefix $(obj)/,$(libfdt_objs) atags + $(addprefix $(obj)/,$(libfdt_hdrs)) + + ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y) ++CFLAGS_REMOVE_atags_to_fdt.o += -Wframe-larger-than=${CONFIG_FRAME_WARN} ++CFLAGS_atags_to_fdt.o += -Wframe-larger-than=1280 + OBJS += $(libfdt_objs) atags_to_fdt.o + endif + diff --git a/queue-5.4/arm-9109-1-oabi-compat-add-epoll_pwait-handler.patch b/queue-5.4/arm-9109-1-oabi-compat-add-epoll_pwait-handler.patch new file mode 100644 index 00000000000..964e3f20d4c --- /dev/null +++ b/queue-5.4/arm-9109-1-oabi-compat-add-epoll_pwait-handler.patch @@ -0,0 +1,92 @@ +From b6e47f3c11c17965acb2a12001af3b1cd5658f37 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Wed, 11 Aug 2021 08:30:20 +0100 +Subject: ARM: 9109/1: oabi-compat: add epoll_pwait handler + +From: Arnd Bergmann + +commit b6e47f3c11c17965acb2a12001af3b1cd5658f37 upstream. + +The epoll_wait() syscall has a special version for OABI compat +mode to convert the arguments to the EABI structure layout +of the kernel. However, the later epoll_pwait() syscall was +added in arch/arm in linux-2.6.32 without this conversion. + +Use the same kind of handler for both. + +Fixes: 369842658a36 ("ARM: 5677/1: ARM support for TIF_RESTORE_SIGMASK/pselect6/ppoll/epoll_pwait") +Cc: stable@vger.kernel.org +Reviewed-by: Christoph Hellwig +Signed-off-by: Arnd Bergmann +Signed-off-by: Russell King (Oracle) +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/kernel/sys_oabi-compat.c | 38 +++++++++++++++++++++++++++++++++++--- + arch/arm/tools/syscall.tbl | 2 +- + 2 files changed, 36 insertions(+), 4 deletions(-) + +--- a/arch/arm/kernel/sys_oabi-compat.c ++++ b/arch/arm/kernel/sys_oabi-compat.c +@@ -269,9 +269,8 @@ asmlinkage long sys_oabi_epoll_ctl(int e + return ret; + } + +-asmlinkage long sys_oabi_epoll_wait(int epfd, +- struct oabi_epoll_event __user *events, +- int maxevents, int timeout) ++static long do_oabi_epoll_wait(int epfd, struct oabi_epoll_event __user *events, ++ int maxevents, int timeout) + { + struct epoll_event *kbuf; + struct oabi_epoll_event e; +@@ -304,6 +303,39 @@ asmlinkage long sys_oabi_epoll_wait(int + return err ? -EFAULT : ret; + } + ++SYSCALL_DEFINE4(oabi_epoll_wait, int, epfd, ++ struct oabi_epoll_event __user *, events, ++ int, maxevents, int, timeout) ++{ ++ return do_oabi_epoll_wait(epfd, events, maxevents, timeout); ++} ++ ++/* ++ * Implement the event wait interface for the eventpoll file. It is the kernel ++ * part of the user space epoll_pwait(2). ++ */ ++SYSCALL_DEFINE6(oabi_epoll_pwait, int, epfd, ++ struct oabi_epoll_event __user *, events, int, maxevents, ++ int, timeout, const sigset_t __user *, sigmask, ++ size_t, sigsetsize) ++{ ++ int error; ++ ++ /* ++ * If the caller wants a certain signal mask to be set during the wait, ++ * we apply it here. ++ */ ++ error = set_user_sigmask(sigmask, sigsetsize); ++ if (error) ++ return error; ++ ++ error = do_oabi_epoll_wait(epfd, events, maxevents, timeout); ++ restore_saved_sigmask_unless(error == -EINTR); ++ ++ return error; ++} ++#endif ++ + struct oabi_sembuf { + unsigned short sem_num; + short sem_op; +--- a/arch/arm/tools/syscall.tbl ++++ b/arch/arm/tools/syscall.tbl +@@ -360,7 +360,7 @@ + 343 common vmsplice sys_vmsplice + 344 common move_pages sys_move_pages + 345 common getcpu sys_getcpu +-346 common epoll_pwait sys_epoll_pwait ++346 common epoll_pwait sys_epoll_pwait sys_oabi_epoll_pwait + 347 common kexec_load sys_kexec_load + 348 common utimensat sys_utimensat_time32 + 349 common signalfd sys_signalfd diff --git a/queue-5.4/libata-add-ata_horkage_no_ncq_trim-for-samsung-860-and-870-ssds.patch b/queue-5.4/libata-add-ata_horkage_no_ncq_trim-for-samsung-860-and-870-ssds.patch new file mode 100644 index 00000000000..2257bb7c268 --- /dev/null +++ b/queue-5.4/libata-add-ata_horkage_no_ncq_trim-for-samsung-860-and-870-ssds.patch @@ -0,0 +1,50 @@ +From 8a6430ab9c9c87cb64c512e505e8690bbaee190b Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Mon, 23 Aug 2021 11:52:20 +0200 +Subject: libata: add ATA_HORKAGE_NO_NCQ_TRIM for Samsung 860 and 870 SSDs + +From: Hans de Goede + +commit 8a6430ab9c9c87cb64c512e505e8690bbaee190b upstream. + +Commit ca6bfcb2f6d9 ("libata: Enable queued TRIM for Samsung SSD 860") +limited the existing ATA_HORKAGE_NO_NCQ_TRIM quirk from "Samsung SSD 8*", +covering all Samsung 800 series SSDs, to only apply to "Samsung SSD 840*" +and "Samsung SSD 850*" series based on information from Samsung. + +But there is a large number of users which is still reporting issues +with the Samsung 860 and 870 SSDs combined with Intel, ASmedia or +Marvell SATA controllers and all reporters also report these problems +going away when disabling queued trims. + +Note that with AMD SATA controllers users are reporting even worse +issues and only completely disabling NCQ helps there, this will be +addressed in a separate patch. + +Fixes: ca6bfcb2f6d9 ("libata: Enable queued TRIM for Samsung SSD 860") +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=203475 +Cc: stable@vger.kernel.org +Cc: Kate Hsuan +Signed-off-by: Hans de Goede +Reviewed-by: Damien Le Moal +Reviewed-by: Martin K. Petersen +Link: https://lore.kernel.org/r/20210823095220.30157-1-hdegoede@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ata/libata-core.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -4556,6 +4556,10 @@ static const struct ata_blacklist_entry + ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "Samsung SSD 850*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | + ATA_HORKAGE_ZERO_AFTER_TRIM, }, ++ { "Samsung SSD 860*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | ++ ATA_HORKAGE_ZERO_AFTER_TRIM, }, ++ { "Samsung SSD 870*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | ++ ATA_HORKAGE_ZERO_AFTER_TRIM, }, + { "FCCT*M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | + ATA_HORKAGE_ZERO_AFTER_TRIM, }, + diff --git a/queue-5.4/pci-aardvark-fix-checking-for-pio-status.patch b/queue-5.4/pci-aardvark-fix-checking-for-pio-status.patch new file mode 100644 index 00000000000..eb6f69e0078 --- /dev/null +++ b/queue-5.4/pci-aardvark-fix-checking-for-pio-status.patch @@ -0,0 +1,162 @@ +From fcb461e2bc8b83b7eaca20cb2221e8b940f2189c Mon Sep 17 00:00:00 2001 +From: Evan Wang +Date: Thu, 22 Jul 2021 16:40:38 +0200 +Subject: PCI: aardvark: Fix checking for PIO status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Evan Wang + +commit fcb461e2bc8b83b7eaca20cb2221e8b940f2189c upstream. + +There is an issue that when PCIe switch is connected to an Armada 3700 +board, there will be lots of warnings about PIO errors when reading the +config space. According to Aardvark PIO read and write sequence in HW +specification, the current way to check PIO status has the following +issues: + +1) For PIO read operation, it reports the error message, which should be + avoided according to HW specification. + +2) For PIO read and write operations, it only checks PIO operation complete + status, which is not enough, and error status should also be checked. + +This patch aligns the code with Aardvark PIO read and write sequence in HW +specification on PIO status check and fix the warnings when reading config +space. + +[pali: Fix CRS handling when CRSSVE is not enabled] + +Link: https://lore.kernel.org/r/20210722144041.12661-2-pali@kernel.org +Tested-by: Victor Gu +Signed-off-by: Evan Wang +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Victor Gu +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # b1bd5714472c ("PCI: aardvark: Indicate error in 'val' when config read fails") +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pci-aardvark.c | 62 +++++++++++++++++++++++++++++----- + 1 file changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -62,6 +62,7 @@ + #define PIO_COMPLETION_STATUS_CRS 2 + #define PIO_COMPLETION_STATUS_CA 4 + #define PIO_NON_POSTED_REQ BIT(10) ++#define PIO_ERR_STATUS BIT(11) + #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) + #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) + #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) +@@ -363,7 +364,7 @@ static void advk_pcie_setup_hw(struct ad + advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + } + +-static void advk_pcie_check_pio_status(struct advk_pcie *pcie) ++static int advk_pcie_check_pio_status(struct advk_pcie *pcie, u32 *val) + { + struct device *dev = &pcie->pdev->dev; + u32 reg; +@@ -374,14 +375,49 @@ static void advk_pcie_check_pio_status(s + status = (reg & PIO_COMPLETION_STATUS_MASK) >> + PIO_COMPLETION_STATUS_SHIFT; + +- if (!status) +- return; +- ++ /* ++ * According to HW spec, the PIO status check sequence as below: ++ * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, ++ * it still needs to check Error Status(bit11), only when this bit ++ * indicates no error happen, the operation is successful. ++ * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only ++ * means a PIO write error, and for PIO read it is successful with ++ * a read value of 0xFFFFFFFF. ++ * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) ++ * only means a PIO write error, and for PIO read it is successful ++ * with a read value of 0xFFFF0001. ++ * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means ++ * error for both PIO read and PIO write operation. ++ * 5) other errors are indicated as 'unknown'. ++ */ + switch (status) { ++ case PIO_COMPLETION_STATUS_OK: ++ if (reg & PIO_ERR_STATUS) { ++ strcomp_status = "COMP_ERR"; ++ break; ++ } ++ /* Get the read result */ ++ if (val) ++ *val = advk_readl(pcie, PIO_RD_DATA); ++ /* No error */ ++ strcomp_status = NULL; ++ break; + case PIO_COMPLETION_STATUS_UR: + strcomp_status = "UR"; + break; + case PIO_COMPLETION_STATUS_CRS: ++ /* PCIe r4.0, sec 2.3.2, says: ++ * If CRS Software Visibility is not enabled, the Root Complex ++ * must re-issue the Configuration Request as a new Request. ++ * A Root Complex implementation may choose to limit the number ++ * of Configuration Request/CRS Completion Status loops before ++ * determining that something is wrong with the target of the ++ * Request and taking appropriate action, e.g., complete the ++ * Request to the host as a failed transaction. ++ * ++ * To simplify implementation do not re-issue the Configuration ++ * Request and complete the Request as a failed transaction. ++ */ + strcomp_status = "CRS"; + break; + case PIO_COMPLETION_STATUS_CA: +@@ -392,6 +428,9 @@ static void advk_pcie_check_pio_status(s + break; + } + ++ if (!strcomp_status) ++ return 0; ++ + if (reg & PIO_NON_POSTED_REQ) + str_posted = "Non-posted"; + else +@@ -399,6 +438,8 @@ static void advk_pcie_check_pio_status(s + + dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", + str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); ++ ++ return -EFAULT; + } + + static int advk_pcie_wait_pio(struct advk_pcie *pcie) +@@ -625,10 +666,13 @@ static int advk_pcie_rd_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ /* Check PIO status and get the read result */ ++ ret = advk_pcie_check_pio_status(pcie, val); ++ if (ret < 0) { ++ *val = 0xffffffff; ++ return PCIBIOS_SET_FAILED; ++ } + +- /* Get the read result */ +- *val = advk_readl(pcie, PIO_RD_DATA); + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) +@@ -692,7 +736,9 @@ static int advk_pcie_wr_conf(struct pci_ + if (ret < 0) + return PCIBIOS_SET_FAILED; + +- advk_pcie_check_pio_status(pcie); ++ ret = advk_pcie_check_pio_status(pcie, NULL); ++ if (ret < 0) ++ return PCIBIOS_SET_FAILED; + + return PCIBIOS_SUCCESSFUL; + } diff --git a/queue-5.4/pci-aardvark-fix-masking-and-unmasking-legacy-intx-interrupts.patch b/queue-5.4/pci-aardvark-fix-masking-and-unmasking-legacy-intx-interrupts.patch new file mode 100644 index 00000000000..5748f569f69 --- /dev/null +++ b/queue-5.4/pci-aardvark-fix-masking-and-unmasking-legacy-intx-interrupts.patch @@ -0,0 +1,75 @@ +From d212dcee27c1f89517181047e5485fcbba4a25c2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 20 Aug 2021 17:50:20 +0200 +Subject: PCI: aardvark: Fix masking and unmasking legacy INTx interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit d212dcee27c1f89517181047e5485fcbba4a25c2 upstream. + +irq_mask and irq_unmask callbacks need to be properly guarded by raw spin +locks as masking/unmasking procedure needs atomic read-modify-write +operation on hardware register. + +Link: https://lore.kernel.org/r/20210820155020.3000-1-pali@kernel.org +Reported-by: Marc Zyngier +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Acked-by: Marc Zyngier +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pci-aardvark.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -194,6 +194,7 @@ struct advk_pcie { + struct list_head resources; + struct irq_domain *irq_domain; + struct irq_chip irq_chip; ++ raw_spinlock_t irq_lock; + struct irq_domain *msi_domain; + struct irq_domain *msi_inner_domain; + struct irq_chip msi_bottom_irq_chip; +@@ -812,22 +813,28 @@ static void advk_pcie_irq_mask(struct ir + { + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); ++ unsigned long flags; + u32 mask; + ++ raw_spin_lock_irqsave(&pcie->irq_lock, flags); + mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); + mask |= PCIE_ISR1_INTX_ASSERT(hwirq); + advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); ++ raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); + } + + static void advk_pcie_irq_unmask(struct irq_data *d) + { + struct advk_pcie *pcie = d->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(d); ++ unsigned long flags; + u32 mask; + ++ raw_spin_lock_irqsave(&pcie->irq_lock, flags); + mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); + mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); + advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); ++ raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); + } + + static int advk_pcie_irq_map(struct irq_domain *h, +@@ -911,6 +918,8 @@ static int advk_pcie_init_irq_domain(str + struct irq_chip *irq_chip; + int ret = 0; + ++ raw_spin_lock_init(&pcie->irq_lock); ++ + pcie_intc_node = of_get_next_child(node, NULL); + if (!pcie_intc_node) { + dev_err(dev, "No PCIe Intc node found\n"); diff --git a/queue-5.4/pci-aardvark-increase-polling-delay-to-1.5s-while-waiting-for-pio-response.patch b/queue-5.4/pci-aardvark-increase-polling-delay-to-1.5s-while-waiting-for-pio-response.patch new file mode 100644 index 00000000000..9659ad6ef46 --- /dev/null +++ b/queue-5.4/pci-aardvark-increase-polling-delay-to-1.5s-while-waiting-for-pio-response.patch @@ -0,0 +1,55 @@ +From 02bcec3ea5591720114f586960490b04b093a09e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Thu, 22 Jul 2021 16:40:39 +0200 +Subject: PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 02bcec3ea5591720114f586960490b04b093a09e upstream. + +Measurements in different conditions showed that aardvark hardware PIO +response can take up to 1.44s. Increase wait timeout from 1ms to 1.5s to +ensure that we do not miss responses from hardware. After 1.44s hardware +returns errors (e.g. Completer abort). + +The previous two patches fixed checking for PIO status, so now we can use +it to also catch errors which are reported by hardware after 1.44s. + +After applying this patch, kernel can detect and print PIO errors to dmesg: + + [ 6.879999] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100004 + [ 6.896436] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100004 + [ 6.913049] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100010 + [ 6.929663] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100010 + [ 6.953558] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100014 + [ 6.970170] advk-pcie d0070000.pcie: Non-posted PIO Response Status: CA, 0xe00 @ 0x100014 + [ 6.994328] advk-pcie d0070000.pcie: Posted PIO Response Status: COMP_ERR, 0x804 @ 0x100004 + +Without this patch kernel prints only a generic error to dmesg: + + [ 5.246847] advk-pcie d0070000.pcie: config read/write timed out + +Link: https://lore.kernel.org/r/20210722144041.12661-3-pali@kernel.org +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Marek Behún +Cc: stable@vger.kernel.org # 7fbcb5da811b ("PCI: aardvark: Don't rely on jiffies while holding spinlock") +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pci-aardvark.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -177,7 +177,7 @@ + (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) + +-#define PIO_RETRY_CNT 500 ++#define PIO_RETRY_CNT 750000 /* 1.5 s */ + #define PIO_RETRY_DELAY 2 /* 2 us*/ + + #define LINK_WAIT_MAX_RETRIES 10 diff --git a/queue-5.4/pci-portdrv-enable-bandwidth-notification-only-if-port-supports-it.patch b/queue-5.4/pci-portdrv-enable-bandwidth-notification-only-if-port-supports-it.patch new file mode 100644 index 00000000000..656173dad54 --- /dev/null +++ b/queue-5.4/pci-portdrv-enable-bandwidth-notification-only-if-port-supports-it.patch @@ -0,0 +1,51 @@ +From 00823dcbdd415c868390feaca16f0265101efab4 Mon Sep 17 00:00:00 2001 +From: Stuart Hayes +Date: Thu, 13 May 2021 03:03:14 +0530 +Subject: PCI/portdrv: Enable Bandwidth Notification only if port supports it + +From: Stuart Hayes + +commit 00823dcbdd415c868390feaca16f0265101efab4 upstream. + +Previously we assumed that all Root Ports and Switch Downstream Ports +supported Link Bandwidth Notification. Per spec, this is only required +for Ports supporting Links wider than x1 and/or multiple Link speeds +(PCIe r5.0, sec 7.5.3.6). + +Because we assumed all Ports supported it, we tried to set up a Bandwidth +Notification IRQ, which failed for devices that don't support IRQs at all, +which meant pcieport didn't attach to the Port at all. + +Check the Link Bandwidth Notification Capability bit and enable the service +only when the Port supports it. + +[bhelgaas: commit log] +Fixes: e8303bb7a75c ("PCI/LINK: Report degraded links via link bandwidth notification") +Link: https://lore.kernel.org/r/20210512213314.7778-1-stuart.w.hayes@gmail.com +Signed-off-by: Stuart Hayes +Signed-off-by: Bjorn Helgaas +Reviewed-by: Lukas Wunner +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/pcie/portdrv_core.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/pci/pcie/portdrv_core.c ++++ b/drivers/pci/pcie/portdrv_core.c +@@ -255,8 +255,13 @@ static int get_port_device_capability(st + services |= PCIE_PORT_SERVICE_DPC; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || +- pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) +- services |= PCIE_PORT_SERVICE_BWNOTIF; ++ pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { ++ u32 linkcap; ++ ++ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap); ++ if (linkcap & PCI_EXP_LNKCAP_LBNC) ++ services |= PCIE_PORT_SERVICE_BWNOTIF; ++ } + + return services; + } diff --git a/queue-5.4/pci-restrict-asmedia-asm1062-sata-max-payload-size-supported.patch b/queue-5.4/pci-restrict-asmedia-asm1062-sata-max-payload-size-supported.patch new file mode 100644 index 00000000000..b61d86d763c --- /dev/null +++ b/queue-5.4/pci-restrict-asmedia-asm1062-sata-max-payload-size-supported.patch @@ -0,0 +1,52 @@ +From b12d93e9958e028856cbcb061b6e64728ca07755 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Thu, 24 Jun 2021 19:14:18 +0200 +Subject: PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Behún + +commit b12d93e9958e028856cbcb061b6e64728ca07755 upstream. + +The ASMedia ASM1062 SATA controller advertises Max_Payload_Size_Supported +of 512, but in fact it cannot handle incoming TLPs with payload size of +512. + +We discovered this issue on PCIe controllers capable of MPS = 512 (Aardvark +and DesignWare), where the issue presents itself as an External Abort. +Bjorn Helgaas says: + + Probably ASM1062 reports a Malformed TLP error when it receives a data + payload of 512 bytes, and Aardvark, DesignWare, etc convert this to an + arm64 External Abort. [1] + +To avoid this problem, limit the ASM1062 Max Payload Size Supported to 256 +bytes, so we set the Max Payload Size of devices that may send TLPs to the +ASM1062 to 256 or less. + +[1] https://lore.kernel.org/linux-pci/20210601170907.GA1949035@bjorn-Precision-5520/ +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=212695 +Link: https://lore.kernel.org/r/20210624171418.27194-2-kabel@kernel.org +Reported-by: Rötti +Signed-off-by: Marek Behún +Signed-off-by: Bjorn Helgaas +Reviewed-by: Krzysztof Wilczyński +Reviewed-by: Pali Rohár +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/quirks.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3252,6 +3252,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SO + PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, + PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); + + /* + * Intel 5000 and 5100 Memory controllers have an erratum with read completion diff --git a/queue-5.4/pci-return-0-data-on-pciconfig_read-cap_sys_admin-failure.patch b/queue-5.4/pci-return-0-data-on-pciconfig_read-cap_sys_admin-failure.patch new file mode 100644 index 00000000000..3ded94fbfb2 --- /dev/null +++ b/queue-5.4/pci-return-0-data-on-pciconfig_read-cap_sys_admin-failure.patch @@ -0,0 +1,56 @@ +From a8bd29bd49c4156ea0ec5a97812333e2aeef44e7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= +Date: Thu, 29 Jul 2021 23:37:54 +0000 +Subject: PCI: Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Krzysztof Wilczyński + +commit a8bd29bd49c4156ea0ec5a97812333e2aeef44e7 upstream. + +The pciconfig_read() syscall reads PCI configuration space using +hardware-dependent config accessors. + +If the read fails on PCI, most accessors don't return an error; they +pretend the read was successful and got ~0 data from the device, so the +syscall returns success with ~0 data in the buffer. + +When the accessor does return an error, pciconfig_read() normally fills the +user's buffer with ~0 and returns an error in errno. But after +e4585da22ad0 ("pci syscall.c: Switch to refcounting API"), we don't fill +the buffer with ~0 for the EPERM "user lacks CAP_SYS_ADMIN" error. + +Userspace may rely on the ~0 data to detect errors, but after e4585da22ad0, +that would not detect CAP_SYS_ADMIN errors. + +Restore the original behaviour of filling the buffer with ~0 when the +CAP_SYS_ADMIN check fails. + +[bhelgaas: commit log, fold in Nathan's fix +https://lore.kernel.org/r/20210803200836.500658-1-nathan@kernel.org] +Fixes: e4585da22ad0 ("pci syscall.c: Switch to refcounting API") +Link: https://lore.kernel.org/r/20210729233755.1509616-1-kw@linux.com +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/syscall.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/pci/syscall.c ++++ b/drivers/pci/syscall.c +@@ -22,8 +22,10 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned + long err; + int cfg_ret; + ++ err = -EPERM; ++ dev = NULL; + if (!capable(CAP_SYS_ADMIN)) +- return -EPERM; ++ goto error; + + err = -ENODEV; + dev = pci_get_domain_bus_and_slot(0, bus, dfn); diff --git a/queue-5.4/pci-xilinx-nwl-enable-the-clock-through-ccf.patch b/queue-5.4/pci-xilinx-nwl-enable-the-clock-through-ccf.patch new file mode 100644 index 00000000000..701f476f3e3 --- /dev/null +++ b/queue-5.4/pci-xilinx-nwl-enable-the-clock-through-ccf.patch @@ -0,0 +1,62 @@ +From de0a01f5296651d3a539f2d23d0db8f359483696 Mon Sep 17 00:00:00 2001 +From: Hyun Kwon +Date: Fri, 25 Jun 2021 12:48:23 +0200 +Subject: PCI: xilinx-nwl: Enable the clock through CCF + +From: Hyun Kwon + +commit de0a01f5296651d3a539f2d23d0db8f359483696 upstream. + +Enable PCIe reference clock. There is no remove function that's why +this should be enough for simple operation. +Normally this clock is enabled by default by firmware but there are +usecases where this clock should be enabled by driver itself. +It is also good that PCIe clock is recorded in a clock framework. + +Link: https://lore.kernel.org/r/ee6997a08fab582b1c6de05f8be184f3fe8d5357.1624618100.git.michal.simek@xilinx.com +Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller") +Signed-off-by: Hyun Kwon +Signed-off-by: Bharat Kumar Gogada +Signed-off-by: Michal Simek +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-xilinx-nwl.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/pci/controller/pcie-xilinx-nwl.c ++++ b/drivers/pci/controller/pcie-xilinx-nwl.c +@@ -6,6 +6,7 @@ + * (C) Copyright 2014 - 2015, Xilinx, Inc. + */ + ++#include + #include + #include + #include +@@ -169,6 +170,7 @@ struct nwl_pcie { + u8 root_busno; + struct nwl_msi msi; + struct irq_domain *legacy_irq_domain; ++ struct clk *clk; + raw_spinlock_t leg_mask_lock; + }; + +@@ -839,6 +841,16 @@ static int nwl_pcie_probe(struct platfor + return err; + } + ++ pcie->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(pcie->clk)) ++ return PTR_ERR(pcie->clk); ++ ++ err = clk_prepare_enable(pcie->clk); ++ if (err) { ++ dev_err(dev, "can't enable PCIe ref clock\n"); ++ return err; ++ } ++ + err = nwl_pcie_bridge_init(pcie); + if (err) { + dev_err(dev, "HW Initialization failed\n"); diff --git a/queue-5.4/series b/queue-5.4/series index 7b58eb2451c..4bf7c8a93af 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -25,3 +25,13 @@ media-uvc-don-t-do-dma-on-stack.patch media-rc-loopback-return-number-of-emitters-rather-than-error.patch revert-dmaengine-imx-sdma-refine-to-load-context-only-once.patch dmaengine-imx-sdma-remove-duplicated-sdma_load_context.patch +libata-add-ata_horkage_no_ncq_trim-for-samsung-860-and-870-ssds.patch +arm-9105-1-atags_to_fdt-don-t-warn-about-stack-size.patch +arm-9109-1-oabi-compat-add-epoll_pwait-handler.patch +pci-portdrv-enable-bandwidth-notification-only-if-port-supports-it.patch +pci-restrict-asmedia-asm1062-sata-max-payload-size-supported.patch +pci-return-0-data-on-pciconfig_read-cap_sys_admin-failure.patch +pci-xilinx-nwl-enable-the-clock-through-ccf.patch +pci-aardvark-fix-checking-for-pio-status.patch +pci-aardvark-increase-polling-delay-to-1.5s-while-waiting-for-pio-response.patch +pci-aardvark-fix-masking-and-unmasking-legacy-intx-interrupts.patch