From: Filip Navara <filip.navara@gmail.com>
Date: Thu, 15 Oct 2009 10:55:26 +0000 (+0200)
Subject: target-arm: fix TANDC and TORC instructions
X-Git-Tag: v0.12.0-rc0~652
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=15bb4eac129931329e3b4d1493331b780d2a92f4;p=thirdparty%2Fqemu.git

target-arm: fix TANDC and TORC instructions

Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 8c5afb72340..454d67f9a89 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1898,6 +1898,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
         if ((insn & 0x000ff00f) != 0x0003f000)
             return 1;
         gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
+        gen_op_movl_T0_T1();
         switch ((insn >> 22) & 3) {
         case 0:
             for (i = 0; i < 7; i ++) {
@@ -1944,6 +1945,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
         if ((insn & 0x000ff00f) != 0x0003f000)
             return 1;
         gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
+        gen_op_movl_T0_T1();
         switch ((insn >> 22) & 3) {
         case 0:
             for (i = 0; i < 7; i ++) {