From: Alvin Lee Date: Tue, 12 May 2020 21:21:54 +0000 (-0400) Subject: drm/amd/display: Disable PG on NV12 X-Git-Tag: v5.9-rc1~134^2~19^2~441 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=15ce104c5a419723f61a186e3711d8e50b131609;p=thirdparty%2Fkernel%2Flinux.git drm/amd/display: Disable PG on NV12 [Why] HW team request to disable PG on NV12 (fixing missed cases) [How] Disable dpp and hubp PG Signed-off-by: Alvin Lee Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 99925079a55de..4ffdbcbcdfd46 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -4053,8 +4053,12 @@ static bool dcn20_resource_construct( // to be consumed. We could have created dcn20_init_hw to get // the same effect by checking ASIC rev, but there was a // request at some point to not check ASIC rev on hw sequencer. - if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) + if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { dc->hwseq->funcs.enable_power_gating_plane = NULL; + dc->debug.disable_dpp_power_gate = true; + dc->debug.disable_hubp_power_gate = true; + } + dc->caps.max_planes = pool->base.pipe_count;