From: Greg Kroah-Hartman Date: Sat, 3 Apr 2021 09:30:09 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v4.4.265~40 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1707c742ba966e10f052d51133776e96824f5bb4;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch pinctrl-rockchip-fix-restore-error-in-resume.patch vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch --- diff --git a/queue-5.4/drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch b/queue-5.4/drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch new file mode 100644 index 00000000000..b9b5771e22b --- /dev/null +++ b/queue-5.4/drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch @@ -0,0 +1,57 @@ +From ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 Mon Sep 17 00:00:00 2001 +From: Thierry Reding +Date: Fri, 19 Mar 2021 14:17:22 +0100 +Subject: drm/tegra: sor: Grab runtime PM reference across reset + +From: Thierry Reding + +commit ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 upstream. + +The SOR resets are exclusively shared with the SOR power domain. This +means that exclusive access can only be granted temporarily and in order +for that to work, a rigorous sequence must be observed. To ensure that a +single consumer gets exclusive access to a reset, each consumer must +implement a rigorous protocol using the reset_control_acquire() and +reset_control_release() functions. + +However, these functions alone don't provide any guarantees at the +system level. Drivers need to ensure that the only a single consumer has +access to the reset at the same time. In order for the SOR to be able to +exclusively access its reset, it must therefore ensure that the SOR +power domain is not powered off by holding on to a runtime PM reference +to that power domain across the reset assert/deassert operation. + +This used to work fine by accident, but was revealed when recently more +devices started to rely on the SOR power domain. + +Fixes: 11c632e1cfd3 ("drm/tegra: sor: Implement acquire/release for reset") +Reported-by: Jonathan Hunter +Signed-off-by: Thierry Reding +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/tegra/sor.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/tegra/sor.c ++++ b/drivers/gpu/drm/tegra/sor.c +@@ -2871,6 +2871,12 @@ static int tegra_sor_init(struct host1x_ + * kernel is possible. + */ + if (sor->rst) { ++ err = pm_runtime_resume_and_get(sor->dev); ++ if (err < 0) { ++ dev_err(sor->dev, "failed to get runtime PM: %d\n", err); ++ return err; ++ } ++ + err = reset_control_acquire(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to acquire SOR reset: %d\n", +@@ -2904,6 +2910,7 @@ static int tegra_sor_init(struct host1x_ + } + + reset_control_release(sor->rst); ++ pm_runtime_put(sor->dev); + } + + err = clk_prepare_enable(sor->clk_safe); diff --git a/queue-5.4/pinctrl-rockchip-fix-restore-error-in-resume.patch b/queue-5.4/pinctrl-rockchip-fix-restore-error-in-resume.patch new file mode 100644 index 00000000000..e84ff7e71c9 --- /dev/null +++ b/queue-5.4/pinctrl-rockchip-fix-restore-error-in-resume.patch @@ -0,0 +1,47 @@ +From c971af25cda94afe71617790826a86253e88eab0 Mon Sep 17 00:00:00 2001 +From: Wang Panzhenzhuan +Date: Tue, 23 Feb 2021 18:07:25 +0800 +Subject: pinctrl: rockchip: fix restore error in resume + +From: Wang Panzhenzhuan + +commit c971af25cda94afe71617790826a86253e88eab0 upstream. + +The restore in resume should match to suspend which only set for RK3288 +SoCs pinctrl. + +Fixes: 8dca933127024 ("pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume") +Reviewed-by: Jianqun Xu +Reviewed-by: Heiko Stuebner +Signed-off-by: Wang Panzhenzhuan +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210223100725.269240-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-rockchip.c | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -3386,12 +3386,15 @@ static int __maybe_unused rockchip_pinct + static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) + { + struct rockchip_pinctrl *info = dev_get_drvdata(dev); +- int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, +- rk3288_grf_gpio6c_iomux | +- GPIO6C6_SEL_WRITE_ENABLE); ++ int ret; + +- if (ret) +- return ret; ++ if (info->ctrl->type == RK3288) { ++ ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, ++ rk3288_grf_gpio6c_iomux | ++ GPIO6C6_SEL_WRITE_ENABLE); ++ if (ret) ++ return ret; ++ } + + return pinctrl_force_default(info->pctl_dev); + } diff --git a/queue-5.4/series b/queue-5.4/series index 9c0fa90176e..bccec3e8625 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -51,3 +51,6 @@ mm-fix-race-by-making-init_zero_pfn-early_initcall.patch drm-amdgpu-fix-offset-calculation-in-amdgpu_vm_bo_clear_mappings.patch drm-amdgpu-check-alignment-on-cpu-page-for-bo-map.patch reiserfs-update-reiserfs_xattrs_initialized-condition.patch +drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch +vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch +pinctrl-rockchip-fix-restore-error-in-resume.patch diff --git a/queue-5.4/vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch b/queue-5.4/vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch new file mode 100644 index 00000000000..2f20331f838 --- /dev/null +++ b/queue-5.4/vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch @@ -0,0 +1,40 @@ +From e0146a108ce4d2c22b9510fd12268e3ee72a0161 Mon Sep 17 00:00:00 2001 +From: Jason Gunthorpe +Date: Mon, 29 Mar 2021 16:00:16 -0300 +Subject: vfio/nvlink: Add missing SPAPR_TCE_IOMMU depends + +From: Jason Gunthorpe + +commit e0146a108ce4d2c22b9510fd12268e3ee72a0161 upstream. + +Compiling the nvlink stuff relies on the SPAPR_TCE_IOMMU otherwise there +are compile errors: + + drivers/vfio/pci/vfio_pci_nvlink2.c:101:10: error: implicit declaration of function 'mm_iommu_put' [-Werror,-Wimplicit-function-declaration] + ret = mm_iommu_put(data->mm, data->mem); + +As PPC only defines these functions when the config is set. + +Previously this wasn't a problem by chance as SPAPR_TCE_IOMMU was the only +IOMMU that could have satisfied IOMMU_API on POWERNV. + +Fixes: 179209fa1270 ("vfio: IOMMU_API should be selected") +Reported-by: kernel test robot +Signed-off-by: Jason Gunthorpe +Message-Id: <0-v1-83dba9768fc3+419-vfio_nvlink2_kconfig_jgg@nvidia.com> +Signed-off-by: Alex Williamson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/vfio/pci/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/vfio/pci/Kconfig ++++ b/drivers/vfio/pci/Kconfig +@@ -42,6 +42,6 @@ config VFIO_PCI_IGD + + config VFIO_PCI_NVLINK2 + def_bool y +- depends on VFIO_PCI && PPC_POWERNV ++ depends on VFIO_PCI && PPC_POWERNV && SPAPR_TCE_IOMMU + help + VFIO PCI support for P9 Witherspoon machine with NVIDIA V100 GPUs