From: Greg Kroah-Hartman Date: Sun, 7 Sep 2025 16:21:36 +0000 (+0200) Subject: 6.12-stable patches X-Git-Tag: v5.4.299~7 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=17fdec7bbe3a552b57d1c3ff4752309b16aab085;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: acpi-risc-v-fix-ffh_cppc_csr-error-handling.patch riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_get_smp_processor_id.patch riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_mov64_percpu_reg.patch riscv-only-allow-lto-with-cmodel_medany.patch riscv-use-lw-when-reading-int-cpu-in-asm_per_cpu.patch riscv-use-lw-when-reading-int-cpu-in-new_vmalloc_check.patch --- diff --git a/queue-6.12/acpi-risc-v-fix-ffh_cppc_csr-error-handling.patch b/queue-6.12/acpi-risc-v-fix-ffh_cppc_csr-error-handling.patch new file mode 100644 index 0000000000..7d322fb862 --- /dev/null +++ b/queue-6.12/acpi-risc-v-fix-ffh_cppc_csr-error-handling.patch @@ -0,0 +1,48 @@ +From 5b3706597b90a7b6c9ae148edd07a43531dcd49e Mon Sep 17 00:00:00 2001 +From: Anup Patel +Date: Mon, 18 Aug 2025 20:05:59 +0530 +Subject: ACPI: RISC-V: Fix FFH_CPPC_CSR error handling + +From: Anup Patel + +commit 5b3706597b90a7b6c9ae148edd07a43531dcd49e upstream. + +The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error +code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must +not use sbi_err_map_linux_errno() for FFH_CPPC_CSR. + +Fixes: 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver") +Signed-off-by: Anup Patel +Reviewed-by: Andrew Jones +Reviewed-by: Troy Mitchell +Reviewed-by: Sunil V L +Reviewed-by: Nutty Liu +Reviewed-by: Atish Patra +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20250818143600.894385-2-apatel@ventanamicro.com +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + drivers/acpi/riscv/cppc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/acpi/riscv/cppc.c ++++ b/drivers/acpi/riscv/cppc.c +@@ -121,7 +121,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg + + *val = data.ret.value; + +- return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; ++ return data.ret.error; + } + + return -EINVAL; +@@ -150,7 +150,7 @@ int cpc_write_ffh(int cpu, struct cpc_re + + smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1); + +- return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0; ++ return data.ret.error; + } + + return -EINVAL; diff --git a/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_get_smp_processor_id.patch b/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_get_smp_processor_id.patch new file mode 100644 index 0000000000..febebc862c --- /dev/null +++ b/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_get_smp_processor_id.patch @@ -0,0 +1,38 @@ +From 8a16586fa7b8a01360890d284896b90c217dca44 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= +Date: Tue, 12 Aug 2025 11:02:56 +0200 +Subject: riscv, bpf: use lw when reading int cpu in bpf_get_smp_processor_id +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Radim Krčmář + +commit 8a16586fa7b8a01360890d284896b90c217dca44 upstream. + +emit_ld is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. +The struct currently has a hole after cpu, so little endian accesses +seemed fine. + +Fixes: 2ddec2c80b44 ("riscv, bpf: inline bpf_get_smp_processor_id()") +Cc: stable@vger.kernel.org +Signed-off-by: Radim Krčmář +Reviewed-by: Pu Lehui +Link: https://lore.kernel.org/r/20250812090256.757273-4-rkrcmar@ventanamicro.com +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/net/bpf_jit_comp64.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/net/bpf_jit_comp64.c ++++ b/arch/riscv/net/bpf_jit_comp64.c +@@ -1557,7 +1557,7 @@ int bpf_jit_emit_insn(const struct bpf_i + */ + if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { + /* Load current CPU number in R0 */ +- emit_ld(bpf_to_rv_reg(BPF_REG_0, ctx), offsetof(struct thread_info, cpu), ++ emit_lw(bpf_to_rv_reg(BPF_REG_0, ctx), offsetof(struct thread_info, cpu), + RV_REG_TP, ctx); + break; + } diff --git a/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_mov64_percpu_reg.patch b/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_mov64_percpu_reg.patch new file mode 100644 index 0000000000..4690cf1345 --- /dev/null +++ b/queue-6.12/riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_mov64_percpu_reg.patch @@ -0,0 +1,41 @@ +From ad5348c765914766a98ad26cf7a8c28d51a16bdd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= +Date: Tue, 12 Aug 2025 11:02:55 +0200 +Subject: riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Radim Krčmář + +commit ad5348c765914766a98ad26cf7a8c28d51a16bdd upstream. + +emit_ld is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. +The struct currently has a hole after cpu, so little endian accesses +seemed fine. + +Fixes: 19c56d4e5be1 ("riscv, bpf: add internal-only MOV instruction to resolve per-CPU addrs") +Cc: stable@vger.kernel.org +Signed-off-by: Radim Krčmář +Reviewed-by: Pu Lehui +Acked-by: Björn Töpel +Tested-by: Björn Töpel # QEMU +Reviewed-by: Alexandre Ghiti +Link: https://lore.kernel.org/r/20250812090256.757273-3-rkrcmar@ventanamicro.com +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/net/bpf_jit_comp64.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/net/bpf_jit_comp64.c ++++ b/arch/riscv/net/bpf_jit_comp64.c +@@ -1150,7 +1150,7 @@ int bpf_jit_emit_insn(const struct bpf_i + emit_mv(rd, rs, ctx); + #ifdef CONFIG_SMP + /* Load current CPU number in T1 */ +- emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu), ++ emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu), + RV_REG_TP, ctx); + /* Load address of __per_cpu_offset array in T2 */ + emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); diff --git a/queue-6.12/riscv-only-allow-lto-with-cmodel_medany.patch b/queue-6.12/riscv-only-allow-lto-with-cmodel_medany.patch new file mode 100644 index 0000000000..a6d8d6b109 --- /dev/null +++ b/queue-6.12/riscv-only-allow-lto-with-cmodel_medany.patch @@ -0,0 +1,46 @@ +From 41f9049cff324b7033e6ed1ded7dfff803cf550a Mon Sep 17 00:00:00 2001 +From: Nathan Chancellor +Date: Thu, 10 Jul 2025 13:25:26 -0700 +Subject: riscv: Only allow LTO with CMODEL_MEDANY + +From: Nathan Chancellor + +commit 41f9049cff324b7033e6ed1ded7dfff803cf550a upstream. + +When building with CONFIG_CMODEL_MEDLOW and CONFIG_LTO_CLANG, there is a +series of errors due to some files being unconditionally compiled with +'-mcmodel=medany', mismatching with the rest of the kernel built with +'-mcmodel=medlow': + + ld.lld: error: Function Import: link error: linking module flags 'Code Model': IDs have conflicting values: 'i32 3' from vmlinux.a(init.o at 899908), and 'i32 1' from vmlinux.a(net-traces.o at 1014628) + +Only allow LTO to be performed when CONFIG_CMODEL_MEDANY is enabled to +ensure there will be no code model mismatch errors. An alternative +solution would be disabling LTO for the files with a different code +model than the main kernel like some specialized areas of the kernel do +but doing that for individual files is not as sustainable than +forbidding the combination altogether. + +Cc: stable@vger.kernel.org +Fixes: 021d23428bdb ("RISC-V: build: Allow LTO to be selected") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202506290255.KBVM83vZ-lkp@intel.com/ +Signed-off-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20250710-riscv-restrict-lto-to-medany-v1-1-b1dac9871ecf@kernel.org +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -61,7 +61,7 @@ config RISCV + select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU + select ARCH_SUPPORTS_HUGETLBFS if MMU + # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505 +- select ARCH_SUPPORTS_LTO_CLANG if LLD_VERSION >= 140000 ++ select ARCH_SUPPORTS_LTO_CLANG if LLD_VERSION >= 140000 && CMODEL_MEDANY + select ARCH_SUPPORTS_LTO_CLANG_THIN if LLD_VERSION >= 140000 + select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU + select ARCH_SUPPORTS_PER_VMA_LOCK if MMU diff --git a/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-asm_per_cpu.patch b/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-asm_per_cpu.patch new file mode 100644 index 0000000000..e848c3378c --- /dev/null +++ b/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-asm_per_cpu.patch @@ -0,0 +1,38 @@ +From f4ea67a722e8c9e1fb8109adebb9fb881ff0793a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= +Date: Fri, 25 Jul 2025 18:54:10 +0200 +Subject: riscv: use lw when reading int cpu in asm_per_cpu +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Radim Krčmář + +commit f4ea67a722e8c9e1fb8109adebb9fb881ff0793a upstream. + +REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. +The struct currently has a hole after cpu, so little endian accesses +seemed fine. + +Fixes: be97d0db5f44 ("riscv: VMAP_STACK overflow detection thread-safe") +Cc: stable@vger.kernel.org +Reviewed-by: Alexandre Ghiti +Signed-off-by: Radim Krčmář +Link: https://lore.kernel.org/r/20250725165410.2896641-5-rkrcmar@ventanamicro.com +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/include/asm/asm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/include/asm/asm.h ++++ b/arch/riscv/include/asm/asm.h +@@ -90,7 +90,7 @@ + #endif + + .macro asm_per_cpu dst sym tmp +- REG_L \tmp, TASK_TI_CPU_NUM(tp) ++ lw \tmp, TASK_TI_CPU_NUM(tp) + slli \tmp, \tmp, PER_CPU_OFFSET_SHIFT + la \dst, __per_cpu_offset + add \dst, \dst, \tmp diff --git a/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-new_vmalloc_check.patch b/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-new_vmalloc_check.patch new file mode 100644 index 0000000000..4a3a2de456 --- /dev/null +++ b/queue-6.12/riscv-use-lw-when-reading-int-cpu-in-new_vmalloc_check.patch @@ -0,0 +1,38 @@ +From e108c8a94f3f958c877f6ec7a6052a893ae4aa98 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= +Date: Fri, 25 Jul 2025 18:54:09 +0200 +Subject: riscv: use lw when reading int cpu in new_vmalloc_check +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Radim Krčmář + +commit e108c8a94f3f958c877f6ec7a6052a893ae4aa98 upstream. + +REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide. +The struct currently has a hole after cpu, so little endian accesses +seemed fine. + +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Cc: stable@vger.kernel.org +Reviewed-by: Alexandre Ghiti +Signed-off-by: Radim Krčmář +Link: https://lore.kernel.org/r/20250725165410.2896641-4-rkrcmar@ventanamicro.com +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/kernel/entry.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -46,7 +46,7 @@ + * a0 = &new_vmalloc[BIT_WORD(cpu)] + * a1 = BIT_MASK(cpu) + */ +- REG_L a2, TASK_TI_CPU(tp) ++ lw a2, TASK_TI_CPU(tp) + /* + * Compute the new_vmalloc element position: + * (cpu / 64) * 8 = (cpu >> 6) << 3 diff --git a/queue-6.12/series b/queue-6.12/series index 2c26883269..dcbecdd3f8 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -165,3 +165,9 @@ perf-bpf-utils-harden-get_bpf_prog_info_linear.patch drm-amd-amdgpu-fix-missing-error-return-on-kzalloc-f.patch tools-gpio-remove-the-include-directory-on-make-clea.patch md-prevent-incorrect-update-of-resync-recovery-offse.patch +acpi-risc-v-fix-ffh_cppc_csr-error-handling.patch +riscv-only-allow-lto-with-cmodel_medany.patch +riscv-use-lw-when-reading-int-cpu-in-new_vmalloc_check.patch +riscv-use-lw-when-reading-int-cpu-in-asm_per_cpu.patch +riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_mov64_percpu_reg.patch +riscv-bpf-use-lw-when-reading-int-cpu-in-bpf_get_smp_processor_id.patch