From: Sylwester Nawrocki Date: Wed, 14 Mar 2018 11:32:26 +0000 (+0100) Subject: clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412 X-Git-Tag: v4.17-rc1~18^2~7^4~1^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=182c084da5d1e4d7c02d913de154cf5167521580;p=thirdparty%2Fkernel%2Flinux.git clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412 This additional frequency is required for HDMI audio support on Odroid U3 board. Signed-off-by: Sylwester Nawrocki --- diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index edf125525a369..0421960eb9633 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1319,6 +1319,7 @@ static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = }; static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { + PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690), PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0), PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381), PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),