From: Greg Kroah-Hartman Date: Tue, 19 Nov 2019 06:38:47 +0000 (+0100) Subject: drop broken patches X-Git-Tag: v5.3.12~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1999d0921ce0afa9621cabee34d76fb1ea145a68;p=thirdparty%2Fkernel%2Fstable-queue.git drop broken patches --- diff --git a/queue-4.14/series b/queue-4.14/series index 1239a285ba4..b149806831f 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -18,7 +18,6 @@ input-synaptics-rmi4-clear-irq-enables-for-f54.patch input-synaptics-rmi4-destroy-f54-poller-workqueue-when-removing.patch ib-hfi1-ensure-full-gen3-speed-in-a-gen4-system.patch i2c-acpi-force-bus-speed-to-400khz-if-a-silead-touchscreen-is-present.patch -x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch ecryptfs_lookup_interpose-lower_dentry-d_inode-is-not-stable.patch ecryptfs_lookup_interpose-lower_dentry-d_parent-is-not-stable-either.patch iommu-vt-d-fix-qi_dev_iotlb_pfsid-and-qi_dev_eiotlb_pfsid-macros.patch @@ -237,4 +236,3 @@ fuse-use-read_once-on-congestion_threshold-and-max_b.patch ib-iser-fix-possible-null-deref-at-iser_inv_desc.patch net-phy-mdio-bcm-unimac-mark-pm-functions-as-__maybe.patch memfd-use-radix_tree_deref_slot_protected-to-avoid-the-warning.patch -x86-timer-skip-pit-initialization-on-modern-chipsets.patch diff --git a/queue-4.14/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch b/queue-4.14/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch deleted file mode 100644 index d768449e619..00000000000 --- a/queue-4.14/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fc5db58539b49351e76f19817ed1102bf7c712d0 Mon Sep 17 00:00:00 2001 -From: Kai-Heng Feng -Date: Wed, 16 Oct 2019 18:38:16 +0800 -Subject: x86/quirks: Disable HPET on Intel Coffe Lake platforms - -From: Kai-Heng Feng - -commit fc5db58539b49351e76f19817ed1102bf7c712d0 upstream. - -Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered -PC10, which in consequence marks TSC as unstable because HPET is used as -watchdog clocksource for TSC. - -Harry Pan tried to work around it in the clocksource watchdog code [1] -thereby creating a circular dependency between HPET and TSC. This also -ignores the fact, that HPET is not only unsuitable as watchdog clocksource -on these systems, it becomes unusable in general. - -Disable HPET on affected platforms. - -Suggested-by: Feng Tang -Signed-off-by: Kai-Heng Feng -Signed-off-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203183 -Link: https://lore.kernel.org/lkml/20190516090651.1396-1-harry.pan@intel.com/ [1] -Link: https://lkml.kernel.org/r/20191016103816.30650-1-kai.heng.feng@canonical.com -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/kernel/early-quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/x86/kernel/early-quirks.c -+++ b/arch/x86/kernel/early-quirks.c -@@ -681,6 +681,8 @@ static struct chipset early_qrk[] __init - */ - { PCI_VENDOR_ID_INTEL, 0x0f00, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, -+ { PCI_VENDOR_ID_INTEL, 0x3ec4, -+ PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, - { PCI_VENDOR_ID_BROADCOM, 0x4331, - PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, - {} diff --git a/queue-4.14/x86-timer-skip-pit-initialization-on-modern-chipsets.patch b/queue-4.14/x86-timer-skip-pit-initialization-on-modern-chipsets.patch deleted file mode 100644 index 016aed8b64a..00000000000 --- a/queue-4.14/x86-timer-skip-pit-initialization-on-modern-chipsets.patch +++ /dev/null @@ -1,209 +0,0 @@ -From c8c4076723daca08bf35ccd68f22ea1c6219e207 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Fri, 28 Jun 2019 15:23:07 +0800 -Subject: x86/timer: Skip PIT initialization on modern chipsets - -From: Thomas Gleixner - -commit c8c4076723daca08bf35ccd68f22ea1c6219e207 upstream. - -Recent Intel chipsets including Skylake and ApolloLake have a special -ITSSPRC register which allows the 8254 PIT to be gated. When gated, the -8254 registers can still be programmed as normal, but there are no IRQ0 -timer interrupts. - -Some products such as the Connex L1430 and exone go Rugged E11 use this -register to ship with the PIT gated by default. This causes Linux to fail -to boot: - - Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with - apic=debug and send a report. - -The panic happens before the framebuffer is initialized, so to the user, it -appears as an early boot hang on a black screen. - -Affected products typically have a BIOS option that can be used to enable -the 8254 and make Linux work (Chipset -> South Cluster Configuration -> -Miscellaneous Configuration -> 8254 Clock Gating), however it would be best -to make Linux support the no-8254 case. - -Modern sytems allow to discover the TSC and local APIC timer frequencies, -so the calibration against the PIT is not required. These systems have -always running timers and the local APIC timer works also in deep power -states. - -So the setup of the PIT including the IO-APIC timer interrupt delivery -checks are a pointless exercise. - -Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, -which avoids the panic caused by non ticking PITs and also speeds up the -boot process. - -Thanks to Daniel for providing the changelog, initial analysis of the -problem and testing against a variety of machines. - -Reported-by: Daniel Drake -Signed-off-by: Thomas Gleixner -Tested-by: Daniel Drake -Cc: bp@alien8.de -Cc: hpa@zytor.com -Cc: linux@endlessm.com -Cc: rafael.j.wysocki@intel.com -Cc: hdegoede@redhat.com -Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com -Cc: Kai-Heng Feng -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/include/asm/apic.h | 2 ++ - arch/x86/include/asm/time.h | 1 + - arch/x86/kernel/apic/apic.c | 27 +++++++++++++++++++++++++++ - arch/x86/kernel/apic/io_apic.c | 4 ++++ - arch/x86/kernel/i8253.c | 25 ++++++++++++++++++++++++- - arch/x86/kernel/time.c | 7 +++++-- - 6 files changed, 63 insertions(+), 3 deletions(-) - ---- a/arch/x86/include/asm/apic.h -+++ b/arch/x86/include/asm/apic.h -@@ -162,6 +162,7 @@ static inline int apic_is_clustered_box( - #endif - - extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); -+extern bool apic_needs_pit(void); - - #else /* !CONFIG_X86_LOCAL_APIC */ - static inline void lapic_shutdown(void) { } -@@ -171,6 +172,7 @@ static inline void disable_local_APIC(vo - # define setup_boot_APIC_clock x86_init_noop - # define setup_secondary_APIC_clock x86_init_noop - static inline void lapic_update_tsc_freq(void) { } -+static inline bool apic_needs_pit(void) { return true; } - #endif /* !CONFIG_X86_LOCAL_APIC */ - - #ifdef CONFIG_X86_X2APIC ---- a/arch/x86/include/asm/time.h -+++ b/arch/x86/include/asm/time.h -@@ -7,6 +7,7 @@ - - extern void hpet_time_init(void); - extern void time_init(void); -+extern bool pit_timer_init(void); - - extern struct clock_event_device *global_clock_event; - ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -804,6 +804,33 @@ calibrate_by_pmtimer(long deltapm, long - return 0; - } - -+bool __init apic_needs_pit(void) -+{ -+ /* -+ * If the frequencies are not known, PIT is required for both TSC -+ * and apic timer calibration. -+ */ -+ if (!tsc_khz || !cpu_khz) -+ return true; -+ -+ /* Is there an APIC at all? */ -+ if (!boot_cpu_has(X86_FEATURE_APIC)) -+ return true; -+ -+ /* Deadline timer is based on TSC so no further PIT action required */ -+ if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) -+ return false; -+ -+ /* APIC timer disabled? */ -+ if (disable_apic_timer) -+ return true; -+ /* -+ * The APIC timer frequency is known already, no PIT calibration -+ * required. If unknown, let the PIT be initialized. -+ */ -+ return lapic_timer_period == 0; -+} -+ - static int __init calibrate_APIC_clock(void) - { - struct clock_event_device *levt = this_cpu_ptr(&lapic_events); ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -58,6 +58,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2037,6 +2038,9 @@ static inline void __init check_timer(vo - unsigned long flags; - int no_pin1 = 0; - -+ if (!global_clock_event) -+ return; -+ - local_irq_save(flags); - - /* ---- a/arch/x86/kernel/i8253.c -+++ b/arch/x86/kernel/i8253.c -@@ -8,6 +8,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -18,10 +19,32 @@ - */ - struct clock_event_device *global_clock_event; - --void __init setup_pit_timer(void) -+/* -+ * Modern chipsets can disable the PIT clock which makes it unusable. It -+ * would be possible to enable the clock but the registers are chipset -+ * specific and not discoverable. Avoid the whack a mole game. -+ * -+ * These platforms have discoverable TSC/CPU frequencies but this also -+ * requires to know the local APIC timer frequency as it normally is -+ * calibrated against the PIT interrupt. -+ */ -+static bool __init use_pit(void) - { -+ if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) -+ return true; -+ -+ /* This also returns true when APIC is disabled */ -+ return apic_needs_pit(); -+} -+ -+bool __init pit_timer_init(void) -+{ -+ if (!use_pit()) -+ return false; -+ - clockevent_i8253_init(true); - global_clock_event = &i8253_clockevent; -+ return true; - } - - #ifndef CONFIG_X86_64 ---- a/arch/x86/kernel/time.c -+++ b/arch/x86/kernel/time.c -@@ -78,8 +78,11 @@ static void __init setup_default_timer_i - /* Default timer init function */ - void __init hpet_time_init(void) - { -- if (!hpet_enable()) -- setup_pit_timer(); -+ if (!hpet_enable()) { -+ if (!pit_timer_init()) -+ return; -+ } -+ - setup_default_timer_irq(); - } - diff --git a/queue-4.19/series b/queue-4.19/series index bc8b2479d41..bd0394d5f7c 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -21,7 +21,6 @@ input-synaptics-rmi4-destroy-f54-poller-workqueue-when-removing.patch ib-hfi1-ensure-full-gen3-speed-in-a-gen4-system.patch ib-hfi1-use-a-common-pad-buffer-for-9b-and-16b-packets.patch i2c-acpi-force-bus-speed-to-400khz-if-a-silead-touchscreen-is-present.patch -x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch ecryptfs_lookup_interpose-lower_dentry-d_inode-is-not-stable.patch ecryptfs_lookup_interpose-lower_dentry-d_parent-is-not-stable-either.patch net-ethernet-dwmac-sun8i-use-the-correct-function-in-exit-path.patch @@ -420,4 +419,3 @@ media-ov2680-fix-null-dereference-at-power-on.patch s390-vdso-correct-vdso-mapping-for-compat-tasks.patch net-phy-mdio-bcm-unimac-mark-pm-functions-as-__maybe.patch memfd-use-radix_tree_deref_slot_protected-to-avoid-the-warning.patch -x86-timer-skip-pit-initialization-on-modern-chipsets.patch diff --git a/queue-4.19/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch b/queue-4.19/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch deleted file mode 100644 index a468fa34bd6..00000000000 --- a/queue-4.19/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fc5db58539b49351e76f19817ed1102bf7c712d0 Mon Sep 17 00:00:00 2001 -From: Kai-Heng Feng -Date: Wed, 16 Oct 2019 18:38:16 +0800 -Subject: x86/quirks: Disable HPET on Intel Coffe Lake platforms - -From: Kai-Heng Feng - -commit fc5db58539b49351e76f19817ed1102bf7c712d0 upstream. - -Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered -PC10, which in consequence marks TSC as unstable because HPET is used as -watchdog clocksource for TSC. - -Harry Pan tried to work around it in the clocksource watchdog code [1] -thereby creating a circular dependency between HPET and TSC. This also -ignores the fact, that HPET is not only unsuitable as watchdog clocksource -on these systems, it becomes unusable in general. - -Disable HPET on affected platforms. - -Suggested-by: Feng Tang -Signed-off-by: Kai-Heng Feng -Signed-off-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203183 -Link: https://lore.kernel.org/lkml/20190516090651.1396-1-harry.pan@intel.com/ [1] -Link: https://lkml.kernel.org/r/20191016103816.30650-1-kai.heng.feng@canonical.com -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/kernel/early-quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/x86/kernel/early-quirks.c -+++ b/arch/x86/kernel/early-quirks.c -@@ -707,6 +707,8 @@ static struct chipset early_qrk[] __init - */ - { PCI_VENDOR_ID_INTEL, 0x0f00, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, -+ { PCI_VENDOR_ID_INTEL, 0x3ec4, -+ PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, - { PCI_VENDOR_ID_BROADCOM, 0x4331, - PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, - {} diff --git a/queue-4.19/x86-timer-skip-pit-initialization-on-modern-chipsets.patch b/queue-4.19/x86-timer-skip-pit-initialization-on-modern-chipsets.patch deleted file mode 100644 index d856681b2fb..00000000000 --- a/queue-4.19/x86-timer-skip-pit-initialization-on-modern-chipsets.patch +++ /dev/null @@ -1,209 +0,0 @@ -From c8c4076723daca08bf35ccd68f22ea1c6219e207 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Fri, 28 Jun 2019 15:23:07 +0800 -Subject: x86/timer: Skip PIT initialization on modern chipsets - -From: Thomas Gleixner - -commit c8c4076723daca08bf35ccd68f22ea1c6219e207 upstream. - -Recent Intel chipsets including Skylake and ApolloLake have a special -ITSSPRC register which allows the 8254 PIT to be gated. When gated, the -8254 registers can still be programmed as normal, but there are no IRQ0 -timer interrupts. - -Some products such as the Connex L1430 and exone go Rugged E11 use this -register to ship with the PIT gated by default. This causes Linux to fail -to boot: - - Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with - apic=debug and send a report. - -The panic happens before the framebuffer is initialized, so to the user, it -appears as an early boot hang on a black screen. - -Affected products typically have a BIOS option that can be used to enable -the 8254 and make Linux work (Chipset -> South Cluster Configuration -> -Miscellaneous Configuration -> 8254 Clock Gating), however it would be best -to make Linux support the no-8254 case. - -Modern sytems allow to discover the TSC and local APIC timer frequencies, -so the calibration against the PIT is not required. These systems have -always running timers and the local APIC timer works also in deep power -states. - -So the setup of the PIT including the IO-APIC timer interrupt delivery -checks are a pointless exercise. - -Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, -which avoids the panic caused by non ticking PITs and also speeds up the -boot process. - -Thanks to Daniel for providing the changelog, initial analysis of the -problem and testing against a variety of machines. - -Reported-by: Daniel Drake -Signed-off-by: Thomas Gleixner -Tested-by: Daniel Drake -Cc: bp@alien8.de -Cc: hpa@zytor.com -Cc: linux@endlessm.com -Cc: rafael.j.wysocki@intel.com -Cc: hdegoede@redhat.com -Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com -Cc: Kai-Heng Feng -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/include/asm/apic.h | 2 ++ - arch/x86/include/asm/time.h | 1 + - arch/x86/kernel/apic/apic.c | 27 +++++++++++++++++++++++++++ - arch/x86/kernel/apic/io_apic.c | 4 ++++ - arch/x86/kernel/i8253.c | 25 ++++++++++++++++++++++++- - arch/x86/kernel/time.c | 7 +++++-- - 6 files changed, 63 insertions(+), 3 deletions(-) - ---- a/arch/x86/include/asm/apic.h -+++ b/arch/x86/include/asm/apic.h -@@ -174,6 +174,7 @@ extern void lapic_assign_system_vectors( - extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); - extern void lapic_online(void); - extern void lapic_offline(void); -+extern bool apic_needs_pit(void); - - #else /* !CONFIG_X86_LOCAL_APIC */ - static inline void lapic_shutdown(void) { } -@@ -187,6 +188,7 @@ static inline void init_bsp_APIC(void) { - static inline void apic_intr_mode_init(void) { } - static inline void lapic_assign_system_vectors(void) { } - static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } -+static inline bool apic_needs_pit(void) { return true; } - #endif /* !CONFIG_X86_LOCAL_APIC */ - - #ifdef CONFIG_X86_X2APIC ---- a/arch/x86/include/asm/time.h -+++ b/arch/x86/include/asm/time.h -@@ -7,6 +7,7 @@ - - extern void hpet_time_init(void); - extern void time_init(void); -+extern bool pit_timer_init(void); - - extern struct clock_event_device *global_clock_event; - ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -796,6 +796,33 @@ calibrate_by_pmtimer(long deltapm, long - return 0; - } - -+bool __init apic_needs_pit(void) -+{ -+ /* -+ * If the frequencies are not known, PIT is required for both TSC -+ * and apic timer calibration. -+ */ -+ if (!tsc_khz || !cpu_khz) -+ return true; -+ -+ /* Is there an APIC at all? */ -+ if (!boot_cpu_has(X86_FEATURE_APIC)) -+ return true; -+ -+ /* Deadline timer is based on TSC so no further PIT action required */ -+ if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) -+ return false; -+ -+ /* APIC timer disabled? */ -+ if (disable_apic_timer) -+ return true; -+ /* -+ * The APIC timer frequency is known already, no PIT calibration -+ * required. If unknown, let the PIT be initialized. -+ */ -+ return lapic_timer_period == 0; -+} -+ - static int __init calibrate_APIC_clock(void) - { - struct clock_event_device *levt = this_cpu_ptr(&lapic_events); ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -58,6 +58,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2127,6 +2128,9 @@ static inline void __init check_timer(vo - unsigned long flags; - int no_pin1 = 0; - -+ if (!global_clock_event) -+ return; -+ - local_irq_save(flags); - - /* ---- a/arch/x86/kernel/i8253.c -+++ b/arch/x86/kernel/i8253.c -@@ -8,6 +8,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -18,10 +19,32 @@ - */ - struct clock_event_device *global_clock_event; - --void __init setup_pit_timer(void) -+/* -+ * Modern chipsets can disable the PIT clock which makes it unusable. It -+ * would be possible to enable the clock but the registers are chipset -+ * specific and not discoverable. Avoid the whack a mole game. -+ * -+ * These platforms have discoverable TSC/CPU frequencies but this also -+ * requires to know the local APIC timer frequency as it normally is -+ * calibrated against the PIT interrupt. -+ */ -+static bool __init use_pit(void) - { -+ if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) -+ return true; -+ -+ /* This also returns true when APIC is disabled */ -+ return apic_needs_pit(); -+} -+ -+bool __init pit_timer_init(void) -+{ -+ if (!use_pit()) -+ return false; -+ - clockevent_i8253_init(true); - global_clock_event = &i8253_clockevent; -+ return true; - } - - #ifndef CONFIG_X86_64 ---- a/arch/x86/kernel/time.c -+++ b/arch/x86/kernel/time.c -@@ -81,8 +81,11 @@ static void __init setup_default_timer_i - /* Default timer init function */ - void __init hpet_time_init(void) - { -- if (!hpet_enable()) -- setup_pit_timer(); -+ if (!hpet_enable()) { -+ if (!pit_timer_init()) -+ return; -+ } -+ - setup_default_timer_irq(); - } - diff --git a/queue-4.4/series b/queue-4.4/series index 07efd9ea724..27032a6d0e2 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -3,7 +3,6 @@ ax88172a-fix-information-leak-on-short-answers.patch alsa-usb-audio-fix-missing-error-check-at-mixer-resolution-test.patch alsa-usb-audio-not-submit-urb-for-stopped-endpoint.patch input-ff-memless-kill-timer-in-destroy.patch -x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch ecryptfs_lookup_interpose-lower_dentry-d_inode-is-not-stable.patch ecryptfs_lookup_interpose-lower_dentry-d_parent-is-not-stable-either.patch iommu-vt-d-fix-qi_dev_iotlb_pfsid-and-qi_dev_eiotlb_pfsid-macros.patch @@ -97,4 +96,3 @@ fuse-use-read_once-on-congestion_threshold-and-max_b.patch bluetooth-hci_ldisc-fix-null-pointer-derefence-in-case-of-early-data.patch bluetooth-hci_ldisc-postpone-hci_uart_proto_ready-bit-set-in-hci_uart_set_proto.patch memfd-use-radix_tree_deref_slot_protected-to-avoid-the-warning.patch -x86-timer-skip-pit-initialization-on-modern-chipsets.patch diff --git a/queue-4.4/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch b/queue-4.4/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch deleted file mode 100644 index c1ddf66bb6e..00000000000 --- a/queue-4.4/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fc5db58539b49351e76f19817ed1102bf7c712d0 Mon Sep 17 00:00:00 2001 -From: Kai-Heng Feng -Date: Wed, 16 Oct 2019 18:38:16 +0800 -Subject: x86/quirks: Disable HPET on Intel Coffe Lake platforms - -From: Kai-Heng Feng - -commit fc5db58539b49351e76f19817ed1102bf7c712d0 upstream. - -Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered -PC10, which in consequence marks TSC as unstable because HPET is used as -watchdog clocksource for TSC. - -Harry Pan tried to work around it in the clocksource watchdog code [1] -thereby creating a circular dependency between HPET and TSC. This also -ignores the fact, that HPET is not only unsuitable as watchdog clocksource -on these systems, it becomes unusable in general. - -Disable HPET on affected platforms. - -Suggested-by: Feng Tang -Signed-off-by: Kai-Heng Feng -Signed-off-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203183 -Link: https://lore.kernel.org/lkml/20190516090651.1396-1-harry.pan@intel.com/ [1] -Link: https://lkml.kernel.org/r/20191016103816.30650-1-kai.heng.feng@canonical.com -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/kernel/early-quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/x86/kernel/early-quirks.c -+++ b/arch/x86/kernel/early-quirks.c -@@ -699,6 +699,8 @@ static struct chipset early_qrk[] __init - */ - { PCI_VENDOR_ID_INTEL, 0x0f00, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, -+ { PCI_VENDOR_ID_INTEL, 0x3ec4, -+ PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, - { PCI_VENDOR_ID_BROADCOM, 0x4331, - PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, - {} diff --git a/queue-4.4/x86-timer-skip-pit-initialization-on-modern-chipsets.patch b/queue-4.4/x86-timer-skip-pit-initialization-on-modern-chipsets.patch deleted file mode 100644 index debe1946548..00000000000 --- a/queue-4.4/x86-timer-skip-pit-initialization-on-modern-chipsets.patch +++ /dev/null @@ -1,209 +0,0 @@ -From c8c4076723daca08bf35ccd68f22ea1c6219e207 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Fri, 28 Jun 2019 15:23:07 +0800 -Subject: x86/timer: Skip PIT initialization on modern chipsets - -From: Thomas Gleixner - -commit c8c4076723daca08bf35ccd68f22ea1c6219e207 upstream. - -Recent Intel chipsets including Skylake and ApolloLake have a special -ITSSPRC register which allows the 8254 PIT to be gated. When gated, the -8254 registers can still be programmed as normal, but there are no IRQ0 -timer interrupts. - -Some products such as the Connex L1430 and exone go Rugged E11 use this -register to ship with the PIT gated by default. This causes Linux to fail -to boot: - - Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with - apic=debug and send a report. - -The panic happens before the framebuffer is initialized, so to the user, it -appears as an early boot hang on a black screen. - -Affected products typically have a BIOS option that can be used to enable -the 8254 and make Linux work (Chipset -> South Cluster Configuration -> -Miscellaneous Configuration -> 8254 Clock Gating), however it would be best -to make Linux support the no-8254 case. - -Modern sytems allow to discover the TSC and local APIC timer frequencies, -so the calibration against the PIT is not required. These systems have -always running timers and the local APIC timer works also in deep power -states. - -So the setup of the PIT including the IO-APIC timer interrupt delivery -checks are a pointless exercise. - -Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, -which avoids the panic caused by non ticking PITs and also speeds up the -boot process. - -Thanks to Daniel for providing the changelog, initial analysis of the -problem and testing against a variety of machines. - -Reported-by: Daniel Drake -Signed-off-by: Thomas Gleixner -Tested-by: Daniel Drake -Cc: bp@alien8.de -Cc: hpa@zytor.com -Cc: linux@endlessm.com -Cc: rafael.j.wysocki@intel.com -Cc: hdegoede@redhat.com -Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com -Cc: Kai-Heng Feng -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/include/asm/apic.h | 2 ++ - arch/x86/include/asm/time.h | 1 + - arch/x86/kernel/apic/apic.c | 27 +++++++++++++++++++++++++++ - arch/x86/kernel/apic/io_apic.c | 4 ++++ - arch/x86/kernel/i8253.c | 25 ++++++++++++++++++++++++- - arch/x86/kernel/time.c | 7 +++++-- - 6 files changed, 63 insertions(+), 3 deletions(-) - ---- a/arch/x86/include/asm/apic.h -+++ b/arch/x86/include/asm/apic.h -@@ -157,6 +157,7 @@ static inline int apic_is_clustered_box( - #endif - - extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); -+extern bool apic_needs_pit(void); - - #else /* !CONFIG_X86_LOCAL_APIC */ - static inline void lapic_shutdown(void) { } -@@ -165,6 +166,7 @@ static inline void init_apic_mappings(vo - static inline void disable_local_APIC(void) { } - # define setup_boot_APIC_clock x86_init_noop - # define setup_secondary_APIC_clock x86_init_noop -+static inline bool apic_needs_pit(void) { return true; } - #endif /* !CONFIG_X86_LOCAL_APIC */ - - #ifdef CONFIG_X86_X2APIC ---- a/arch/x86/include/asm/time.h -+++ b/arch/x86/include/asm/time.h -@@ -6,6 +6,7 @@ - - extern void hpet_time_init(void); - extern void time_init(void); -+extern bool pit_timer_init(void); - - extern struct clock_event_device *global_clock_event; - ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -674,6 +674,33 @@ calibrate_by_pmtimer(long deltapm, long - return 0; - } - -+bool __init apic_needs_pit(void) -+{ -+ /* -+ * If the frequencies are not known, PIT is required for both TSC -+ * and apic timer calibration. -+ */ -+ if (!tsc_khz || !cpu_khz) -+ return true; -+ -+ /* Is there an APIC at all? */ -+ if (!boot_cpu_has(X86_FEATURE_APIC)) -+ return true; -+ -+ /* Deadline timer is based on TSC so no further PIT action required */ -+ if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) -+ return false; -+ -+ /* APIC timer disabled? */ -+ if (disable_apic_timer) -+ return true; -+ /* -+ * The APIC timer frequency is known already, no PIT calibration -+ * required. If unknown, let the PIT be initialized. -+ */ -+ return lapic_timer_period == 0; -+} -+ - static int __init calibrate_APIC_clock(void) - { - struct clock_event_device *levt = this_cpu_ptr(&lapic_events); ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -57,6 +57,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2057,6 +2058,9 @@ static inline void __init check_timer(vo - unsigned long flags; - int no_pin1 = 0; - -+ if (!global_clock_event) -+ return; -+ - local_irq_save(flags); - - /* ---- a/arch/x86/kernel/i8253.c -+++ b/arch/x86/kernel/i8253.c -@@ -7,6 +7,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -17,10 +18,32 @@ - */ - struct clock_event_device *global_clock_event; - --void __init setup_pit_timer(void) -+/* -+ * Modern chipsets can disable the PIT clock which makes it unusable. It -+ * would be possible to enable the clock but the registers are chipset -+ * specific and not discoverable. Avoid the whack a mole game. -+ * -+ * These platforms have discoverable TSC/CPU frequencies but this also -+ * requires to know the local APIC timer frequency as it normally is -+ * calibrated against the PIT interrupt. -+ */ -+static bool __init use_pit(void) - { -+ if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) -+ return true; -+ -+ /* This also returns true when APIC is disabled */ -+ return apic_needs_pit(); -+} -+ -+bool __init pit_timer_init(void) -+{ -+ if (!use_pit()) -+ return false; -+ - clockevent_i8253_init(true); - global_clock_event = &i8253_clockevent; -+ return true; - } - - #ifndef CONFIG_X86_64 ---- a/arch/x86/kernel/time.c -+++ b/arch/x86/kernel/time.c -@@ -76,8 +76,11 @@ void __init setup_default_timer_irq(void - /* Default timer init function */ - void __init hpet_time_init(void) - { -- if (!hpet_enable()) -- setup_pit_timer(); -+ if (!hpet_enable()) { -+ if (!pit_timer_init()) -+ return; -+ } -+ - setup_default_timer_irq(); - } - diff --git a/queue-4.9/series b/queue-4.9/series index f66e6c8de03..66206c5ea47 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -7,7 +7,6 @@ input-synaptics-rmi4-fix-video-buffer-size.patch input-synaptics-rmi4-clear-irq-enables-for-f54.patch input-synaptics-rmi4-destroy-f54-poller-workqueue-when-removing.patch ib-hfi1-ensure-full-gen3-speed-in-a-gen4-system.patch -x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch ecryptfs_lookup_interpose-lower_dentry-d_inode-is-not-stable.patch ecryptfs_lookup_interpose-lower_dentry-d_parent-is-not-stable-either.patch iommu-vt-d-fix-qi_dev_iotlb_pfsid-and-qi_dev_eiotlb_pfsid-macros.patch @@ -145,4 +144,3 @@ usb-xhci-mtk-fix-isoc-error-when-interval-is-zero.patch fuse-use-read_once-on-congestion_threshold-and-max_b.patch ib-iser-fix-possible-null-deref-at-iser_inv_desc.patch memfd-use-radix_tree_deref_slot_protected-to-avoid-the-warning.patch -x86-timer-skip-pit-initialization-on-modern-chipsets.patch diff --git a/queue-4.9/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch b/queue-4.9/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch deleted file mode 100644 index 022377508f1..00000000000 --- a/queue-4.9/x86-quirks-disable-hpet-on-intel-coffe-lake-platforms.patch +++ /dev/null @@ -1,44 +0,0 @@ -From fc5db58539b49351e76f19817ed1102bf7c712d0 Mon Sep 17 00:00:00 2001 -From: Kai-Heng Feng -Date: Wed, 16 Oct 2019 18:38:16 +0800 -Subject: x86/quirks: Disable HPET on Intel Coffe Lake platforms - -From: Kai-Heng Feng - -commit fc5db58539b49351e76f19817ed1102bf7c712d0 upstream. - -Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered -PC10, which in consequence marks TSC as unstable because HPET is used as -watchdog clocksource for TSC. - -Harry Pan tried to work around it in the clocksource watchdog code [1] -thereby creating a circular dependency between HPET and TSC. This also -ignores the fact, that HPET is not only unsuitable as watchdog clocksource -on these systems, it becomes unusable in general. - -Disable HPET on affected platforms. - -Suggested-by: Feng Tang -Signed-off-by: Kai-Heng Feng -Signed-off-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203183 -Link: https://lore.kernel.org/lkml/20190516090651.1396-1-harry.pan@intel.com/ [1] -Link: https://lkml.kernel.org/r/20191016103816.30650-1-kai.heng.feng@canonical.com -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/kernel/early-quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/x86/kernel/early-quirks.c -+++ b/arch/x86/kernel/early-quirks.c -@@ -677,6 +677,8 @@ static struct chipset early_qrk[] __init - */ - { PCI_VENDOR_ID_INTEL, 0x0f00, - PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, -+ { PCI_VENDOR_ID_INTEL, 0x3ec4, -+ PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, - { PCI_VENDOR_ID_BROADCOM, 0x4331, - PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, - {} diff --git a/queue-4.9/x86-timer-skip-pit-initialization-on-modern-chipsets.patch b/queue-4.9/x86-timer-skip-pit-initialization-on-modern-chipsets.patch deleted file mode 100644 index bd14d8d0db4..00000000000 --- a/queue-4.9/x86-timer-skip-pit-initialization-on-modern-chipsets.patch +++ /dev/null @@ -1,209 +0,0 @@ -From c8c4076723daca08bf35ccd68f22ea1c6219e207 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Fri, 28 Jun 2019 15:23:07 +0800 -Subject: x86/timer: Skip PIT initialization on modern chipsets - -From: Thomas Gleixner - -commit c8c4076723daca08bf35ccd68f22ea1c6219e207 upstream. - -Recent Intel chipsets including Skylake and ApolloLake have a special -ITSSPRC register which allows the 8254 PIT to be gated. When gated, the -8254 registers can still be programmed as normal, but there are no IRQ0 -timer interrupts. - -Some products such as the Connex L1430 and exone go Rugged E11 use this -register to ship with the PIT gated by default. This causes Linux to fail -to boot: - - Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with - apic=debug and send a report. - -The panic happens before the framebuffer is initialized, so to the user, it -appears as an early boot hang on a black screen. - -Affected products typically have a BIOS option that can be used to enable -the 8254 and make Linux work (Chipset -> South Cluster Configuration -> -Miscellaneous Configuration -> 8254 Clock Gating), however it would be best -to make Linux support the no-8254 case. - -Modern sytems allow to discover the TSC and local APIC timer frequencies, -so the calibration against the PIT is not required. These systems have -always running timers and the local APIC timer works also in deep power -states. - -So the setup of the PIT including the IO-APIC timer interrupt delivery -checks are a pointless exercise. - -Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, -which avoids the panic caused by non ticking PITs and also speeds up the -boot process. - -Thanks to Daniel for providing the changelog, initial analysis of the -problem and testing against a variety of machines. - -Reported-by: Daniel Drake -Signed-off-by: Thomas Gleixner -Tested-by: Daniel Drake -Cc: bp@alien8.de -Cc: hpa@zytor.com -Cc: linux@endlessm.com -Cc: rafael.j.wysocki@intel.com -Cc: hdegoede@redhat.com -Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com -Cc: Kai-Heng Feng -Signed-off-by: Greg Kroah-Hartman - ---- - arch/x86/include/asm/apic.h | 2 ++ - arch/x86/include/asm/time.h | 1 + - arch/x86/kernel/apic/apic.c | 27 +++++++++++++++++++++++++++ - arch/x86/kernel/apic/io_apic.c | 4 ++++ - arch/x86/kernel/i8253.c | 25 ++++++++++++++++++++++++- - arch/x86/kernel/time.c | 7 +++++-- - 6 files changed, 63 insertions(+), 3 deletions(-) - ---- a/arch/x86/include/asm/apic.h -+++ b/arch/x86/include/asm/apic.h -@@ -164,6 +164,7 @@ static inline int apic_is_clustered_box( - #endif - - extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); -+extern bool apic_needs_pit(void); - - #else /* !CONFIG_X86_LOCAL_APIC */ - static inline void lapic_shutdown(void) { } -@@ -173,6 +174,7 @@ static inline void disable_local_APIC(vo - # define setup_boot_APIC_clock x86_init_noop - # define setup_secondary_APIC_clock x86_init_noop - static inline void lapic_update_tsc_freq(void) { } -+static inline bool apic_needs_pit(void) { return true; } - #endif /* !CONFIG_X86_LOCAL_APIC */ - - #ifdef CONFIG_X86_X2APIC ---- a/arch/x86/include/asm/time.h -+++ b/arch/x86/include/asm/time.h -@@ -6,6 +6,7 @@ - - extern void hpet_time_init(void); - extern void time_init(void); -+extern bool pit_timer_init(void); - - extern struct clock_event_device *global_clock_event; - ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -710,6 +710,33 @@ calibrate_by_pmtimer(long deltapm, long - return 0; - } - -+bool __init apic_needs_pit(void) -+{ -+ /* -+ * If the frequencies are not known, PIT is required for both TSC -+ * and apic timer calibration. -+ */ -+ if (!tsc_khz || !cpu_khz) -+ return true; -+ -+ /* Is there an APIC at all? */ -+ if (!boot_cpu_has(X86_FEATURE_APIC)) -+ return true; -+ -+ /* Deadline timer is based on TSC so no further PIT action required */ -+ if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) -+ return false; -+ -+ /* APIC timer disabled? */ -+ if (disable_apic_timer) -+ return true; -+ /* -+ * The APIC timer frequency is known already, no PIT calibration -+ * required. If unknown, let the PIT be initialized. -+ */ -+ return lapic_timer_period == 0; -+} -+ - static int __init calibrate_APIC_clock(void) - { - struct clock_event_device *levt = this_cpu_ptr(&lapic_events); ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -58,6 +58,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2059,6 +2060,9 @@ static inline void __init check_timer(vo - unsigned long flags; - int no_pin1 = 0; - -+ if (!global_clock_event) -+ return; -+ - local_irq_save(flags); - - /* ---- a/arch/x86/kernel/i8253.c -+++ b/arch/x86/kernel/i8253.c -@@ -7,6 +7,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -17,10 +18,32 @@ - */ - struct clock_event_device *global_clock_event; - --void __init setup_pit_timer(void) -+/* -+ * Modern chipsets can disable the PIT clock which makes it unusable. It -+ * would be possible to enable the clock but the registers are chipset -+ * specific and not discoverable. Avoid the whack a mole game. -+ * -+ * These platforms have discoverable TSC/CPU frequencies but this also -+ * requires to know the local APIC timer frequency as it normally is -+ * calibrated against the PIT interrupt. -+ */ -+static bool __init use_pit(void) - { -+ if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) -+ return true; -+ -+ /* This also returns true when APIC is disabled */ -+ return apic_needs_pit(); -+} -+ -+bool __init pit_timer_init(void) -+{ -+ if (!use_pit()) -+ return false; -+ - clockevent_i8253_init(true); - global_clock_event = &i8253_clockevent; -+ return true; - } - - #ifndef CONFIG_X86_64 ---- a/arch/x86/kernel/time.c -+++ b/arch/x86/kernel/time.c -@@ -77,8 +77,11 @@ void __init setup_default_timer_irq(void - /* Default timer init function */ - void __init hpet_time_init(void) - { -- if (!hpet_enable()) -- setup_pit_timer(); -+ if (!hpet_enable()) { -+ if (!pit_timer_init()) -+ return; -+ } -+ - setup_default_timer_irq(); - } -