From: Tao Zhang Date: Sun, 4 Feb 2024 05:30:40 +0000 (+0800) Subject: dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register X-Git-Tag: v6.9-rc1~35^2~68^2~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=19bfaff3845727f354079a140f092336d97e5c1e;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) for TPDM. It specifies the number of CMB MSR registers supported by the TDPM. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1707024641-22460-10-git-send-email-quic_taozha@quicinc.com --- diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 2320b54459006..d0647ffaed71e 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -69,6 +69,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msrs-num: + description: + Specifies the number of CMB MSR(mux select register) registers supported + by the monitor. If this property is not configured or set to 0, it means + this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -123,6 +132,7 @@ examples: reg = <0x06c29000 0x1000>; qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";