From: eopXD Date: Mon, 20 Jun 2022 06:51:11 +0000 (+0000) Subject: target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior X-Git-Tag: v7.2.0-rc0~92^2~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1ad3f9bdc76c83b23d689a111d5a160c528ac8ba;p=thirdparty%2Fqemu.git target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This commit adds option 'rvv_ma_all_1s' is added to enable the behavior, it is default as disabled. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <165570784143.17634.35095816584573691-10@git.sr.ht> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 117d308ae56..966e5f2dd7e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1061,6 +1061,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), + DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), DEFINE_PROP_END_OF_LIST(), };