From: Tom Rini Date: Tue, 19 Aug 2025 17:26:39 +0000 (-0600) Subject: Merge patch series "ram: k3-ddrss: Support partial inline ECC" X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1ad89bfe1a8d67adc987ffc916fbdcad6192fb4a;p=thirdparty%2Fu-boot.git Merge patch series "ram: k3-ddrss: Support partial inline ECC" Neha Malcom Francis says: Currently, the inline ECC implementation enables inline ECC across the entire DDR space. However this is not always required and a more common ask is to have only a portion of the DDR protected as enabling ECC impacts read/write performance metrics. This series aims to modify the logic to firstly support partial inline ECC in its' most basic form which works for single controllers. Then it introduces an algorithm to support multi DDR controllers where interleaving plays a role. Since interleaving is handled by the MSMC, it only makes sense to have the MSMC decide the inline ECC ranges for each DDR. This series also introduces support for multiple partial regions of inline ECC however due to complexity only support for single DDR is present now. WIP: A commandline test case patch for verifying the correct behaviour of inline ECC including partial case. Was targeted for v2 however a little tricky to make it a general test case especially for multi-DDR cases, so have not combined it in this series for now. Testing: - Memtester runs for J721S2 and J784S4 platforms with and without ECC enablement runs fine. - Along with patches that add support for the commandline test (see WIP note above) J784S4 shows expected behavior for three sets of partial inline ECC regions (non-overlapping, and after modifying J784S4 to have single DDR instead of multi-DDR): https://gist.github.com/nehamalcom/bde7e14e96485e4a188c3af3af6d75d6 Link: https://lore.kernel.org/r/20250812124324.124306-1-n-francis@ti.com --- 1ad89bfe1a8d67adc987ffc916fbdcad6192fb4a