From: Oliver Upton <oliver.upton@linux.dev>
Date: Wed, 19 Mar 2025 21:53:54 +0000 (-0700)
Subject: Merge branch 'kvm-arm64/pmuv3-asahi' into kvmarm/next
X-Git-Tag: v6.15-rc1~195^2~2^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1b1d1b17b8775f58215b166e24d931890682608e;p=thirdparty%2Fkernel%2Flinux.git

Merge branch 'kvm-arm64/pmuv3-asahi' into kvmarm/next

* kvm-arm64/pmuv3-asahi:
  : Support PMUv3 for KVM guests on Apple silicon
  :
  : Take advantage of some IMPLEMENTATION DEFINED traps available on Apple
  : parts to trap-and-emulate the PMUv3 registers on behalf of a KVM guest.
  : Constrain the vPMU to a cycle counter and single event counter, as the
  : Apple PMU has events that cannot be counted on every counter.
  :
  : There is a small new interface between the ARM PMU driver and KVM, where
  : the PMU driver owns the PMUv3 -> hardware event mappings.
  arm64: Enable IMP DEF PMUv3 traps on Apple M*
  KVM: arm64: Provide 1 event counter on IMPDEF hardware
  drivers/perf: apple_m1: Provide helper for mapping PMUv3 events
  KVM: arm64: Remap PMUv3 events onto hardware
  KVM: arm64: Advertise PMUv3 if IMPDEF traps are present
  KVM: arm64: Compute synthetic sysreg ESR for Apple PMUv3 traps
  KVM: arm64: Move PMUVer filtering into KVM code
  KVM: arm64: Use guard() to cleanup usage of arm_pmus_lock
  KVM: arm64: Drop kvm_arm_pmu_available static key
  KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3
  KVM: arm64: Always support SW_INCR PMU event
  KVM: arm64: Compute PMCEID from arm_pmu's event bitmaps
  drivers/perf: apple_m1: Support host/guest event filtering
  drivers/perf: apple_m1: Refactor event select/filter configuration

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---

1b1d1b17b8775f58215b166e24d931890682608e
diff --cc arch/arm64/kernel/cpu_errata.c
index 66869d81c3d54,a1e16b156fab3..b55f5f7057502
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@@ -244,9 -191,46 +244,46 @@@ has_neoverse_n1_erratum_1542419(const s
  	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
  
  	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 -	return is_midr_in_range(midr, &range) && has_dic;
 +	return is_midr_in_range(&range) && has_dic;
  }
  
+ static const struct midr_range impdef_pmuv3_cpus[] = {
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
+ 	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
+ 	{},
+ };
+ 
+ static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope)
+ {
+ 	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+ 	unsigned int pmuver;
+ 
+ 	if (!is_kernel_in_hyp_mode())
+ 		return false;
+ 
+ 	pmuver = cpuid_feature_extract_unsigned_field(dfr0,
+ 						      ID_AA64DFR0_EL1_PMUVer_SHIFT);
+ 	if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
+ 		return false;
+ 
 -	return is_midr_in_range_list(read_cpuid_id(), impdef_pmuv3_cpus);
++	return is_midr_in_range_list(impdef_pmuv3_cpus);
+ }
+ 
+ static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused)
+ {
+ 	sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56));
+ }
+ 
  #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
  static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
  #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009