From: Kito Cheng <kito.cheng@sifive.com>
Date: Fri, 17 Jan 2025 01:53:01 +0000 (+0800)
Subject: RISC-V: Use t2 for tail if Zicfilp enabled
X-Git-Tag: binutils-2_44~72
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1c618df71307a9b1403c55ade463bf23e1d7e770;p=thirdparty%2Fbinutils-gdb.git

RISC-V: Use t2 for tail if Zicfilp enabled

This change is to make tail conform with software guarded jump of Zicfilp. The
reason to not choose t1 as the label register is that t1 is also as .got.plt
offset of _dl_runtime_resolve in PLT.

See more: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93
---

diff --git a/gas/testsuite/gas/riscv/tail.d b/gas/testsuite/gas/riscv/tail.d
new file mode 100644
index 00000000000..6e5db231061
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tail.d
@@ -0,0 +1,13 @@
+#as: -march=rv32gc_zicfiss_zicfilp
+#objdump: -d
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]+[0-9a-f]+:[ 	]+00000317[ 	]+auipc[ 	]+t1,0x0
+[ 	]+[0-9a-f]+:[ 	]+00030067[ 	]+jr[ 	]+t1 # 0 <foo>
+[ 	]+[0-9a-f]+:[ 	]+00000397[ 	]+auipc[ 	]+t2,0x0
+[ 	]+[0-9a-f]+:[ 	]+00038067[ 	]+jr[ 	]+t2 # 8 <foo\+0x8>
diff --git a/gas/testsuite/gas/riscv/tail.s b/gas/testsuite/gas/riscv/tail.s
new file mode 100644
index 00000000000..8058244367b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tail.s
@@ -0,0 +1,9 @@
+foo:
+.option push
+.option arch, rv32i
+	tail foo
+.option pop
+.option push
+.option arch, rv32i_zicfilp
+	tail foo
+.option pop
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ed37eb71bbb..ceb94a563e2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -465,6 +465,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"jal",         0, INSN_CLASS_I, "d,a",       MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR },
 {"call",        0, INSN_CLASS_I, "d,c",       (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"call",        0, INSN_CLASS_I, "c",         (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, NULL, INSN_MACRO },
+{"tail",        0, INSN_CLASS_ZICFILP, "c",   (X_T2 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"tail",        0, INSN_CLASS_I, "c",         (X_T1 << OP_SH_RS1), (int) M_CALL, NULL, INSN_MACRO },
 {"jump",        0, INSN_CLASS_I, "c,s",       0, (int) M_CALL, match_rs1_nonzero, INSN_MACRO },
 {"nop",         0, INSN_CLASS_C, "",          MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },