From: Greg Kroah-Hartman Date: Mon, 19 Jun 2023 08:25:42 +0000 (+0200) Subject: 5.10-stable patches X-Git-Tag: v4.14.319~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1c64b70cb7a7632036598f5a3890ffe3145f21b5;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: drm-i915-dg1-wait-for-pcode-uncore-handshake-at-startup.patch drm-i915-gen11-only-load-dram-information-from-pcode.patch --- diff --git a/queue-5.10/drm-i915-dg1-wait-for-pcode-uncore-handshake-at-startup.patch b/queue-5.10/drm-i915-dg1-wait-for-pcode-uncore-handshake-at-startup.patch new file mode 100644 index 00000000000..f129f614ea0 --- /dev/null +++ b/queue-5.10/drm-i915-dg1-wait-for-pcode-uncore-handshake-at-startup.patch @@ -0,0 +1,104 @@ +From henning.schild@siemens.com Thu Jun 15 13:39:23 2023 +From: Henning Schild +Date: Thu, 15 Jun 2023 13:39:08 +0200 +Subject: drm/i915/dg1: Wait for pcode/uncore handshake at startup +To: , Greg Kroah-Hartman +Cc: holger.philipps@siemens.com, wagner.dominik@siemens.com, "José Roberto de Souza" , "Matt Roper" , "Clinton Taylor" , "Ville Syrjälä" , "Radhakrishna Sripada" , "Lucas De Marchi" , "Henning Schild" +Message-ID: <20230615113909.2109-2-henning.schild@siemens.com> + +From: Matt Roper + +[ Upstream commit f9c730ede7d3f40900cb493890d94d868ff2f00f ] + +DG1 does some additional pcode/uncore handshaking at +boot time; this handshaking must complete before various other pcode +commands are effective and before general work is submitted to the GPU. +We need to poll a new pcode mailbox during startup until it reports that +this handshaking is complete. + +The bspec doesn't give guidance on how long we may need to wait for this +handshaking to complete. For now, let's just set a really long timeout; +if we still don't get a completion status by the end of that timeout, +we'll just continue on and hope for the best. + +v2 (Lucas): Rename macros to make clear the relation between command and + result (requested by José) + +Bspec: 52065 +Cc: Clinton Taylor +Cc: Ville Syrjälä +Cc: Radhakrishna Sripada +Signed-off-by: Matt Roper +Signed-off-by: Lucas De Marchi +Reviewed-by: José Roberto de Souza +Link: https://patchwork.freedesktop.org/patch/msgid/20201001063917.3133475-2-lucas.demarchi@intel.com +Signed-off-by: Henning Schild +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/i915_drv.c | 3 +++ + drivers/gpu/drm/i915/i915_reg.h | 3 +++ + drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++ + drivers/gpu/drm/i915/intel_sideband.h | 2 ++ + 4 files changed, 23 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_drv.c ++++ b/drivers/gpu/drm/i915/i915_drv.c +@@ -84,6 +84,7 @@ + #include "intel_gvt.h" + #include "intel_memory_region.h" + #include "intel_pm.h" ++#include "intel_sideband.h" + #include "vlv_suspend.h" + + static struct drm_driver driver; +@@ -614,6 +615,8 @@ static int i915_driver_hw_probe(struct d + */ + intel_dram_detect(dev_priv); + ++ intel_pcode_init(dev_priv); ++ + intel_bw_init_hw(dev_priv); + + return 0; +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -9235,6 +9235,9 @@ enum { + #define GEN9_SAGV_DISABLE 0x0 + #define GEN9_SAGV_IS_DISABLED 0x1 + #define GEN9_SAGV_ENABLE 0x3 ++#define DG1_PCODE_STATUS 0x7E ++#define DG1_UNCORE_GET_INIT_STATUS 0x0 ++#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 + #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 + #define GEN6_PCODE_DATA _MMIO(0x138128) + #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +--- a/drivers/gpu/drm/i915/intel_sideband.c ++++ b/drivers/gpu/drm/i915/intel_sideband.c +@@ -555,3 +555,18 @@ out: + return ret ? ret : status; + #undef COND + } ++ ++void intel_pcode_init(struct drm_i915_private *i915) ++{ ++ int ret; ++ ++ if (!IS_DGFX(i915)) ++ return; ++ ++ ret = skl_pcode_request(i915, DG1_PCODE_STATUS, ++ DG1_UNCORE_GET_INIT_STATUS, ++ DG1_UNCORE_INIT_STATUS_COMPLETE, ++ DG1_UNCORE_INIT_STATUS_COMPLETE, 50); ++ if (ret) ++ drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n"); ++} +--- a/drivers/gpu/drm/i915/intel_sideband.h ++++ b/drivers/gpu/drm/i915/intel_sideband.h +@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(stru + int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request, + u32 reply_mask, u32 reply, int timeout_base_ms); + ++void intel_pcode_init(struct drm_i915_private *i915); ++ + #endif /* _INTEL_SIDEBAND_H */ diff --git a/queue-5.10/drm-i915-gen11-only-load-dram-information-from-pcode.patch b/queue-5.10/drm-i915-gen11-only-load-dram-information-from-pcode.patch new file mode 100644 index 00000000000..91dc0182d83 --- /dev/null +++ b/queue-5.10/drm-i915-gen11-only-load-dram-information-from-pcode.patch @@ -0,0 +1,292 @@ +From henning.schild@siemens.com Thu Jun 15 13:39:23 2023 +From: Henning Schild +Date: Thu, 15 Jun 2023 13:39:09 +0200 +Subject: drm/i915/gen11+: Only load DRAM information from pcode +To: , Greg Kroah-Hartman +Cc: holger.philipps@siemens.com, wagner.dominik@siemens.com, "José Roberto de Souza" , "Matt Roper" , "Lucas De Marchi" , "Henning Schild" +Message-ID: <20230615113909.2109-3-henning.schild@siemens.com> + +From: José Roberto de Souza + +[ Upstream commit 5d0c938ec9cc96fc7b8abcff0ca8b2a084e9c90c ] + +Up to now we were reading some DRAM information from MCHBAR register +and from pcode what is already not good but some GEN12(TGL-H and ADL-S) +platforms have MCHBAR DRAM information in different offsets. + +This was notified to HW team that decided that the best alternative is +always apply the 16gb_dimm watermark adjustment for GEN12+ platforms +and read the remaning DRAM information needed to other display +programming from pcode. + +So here moving the DRAM pcode function to intel_dram.c, removing +the duplicated fields from intel_qgv_info, setting and using +information from dram_info. + +v2: +- bring back num_points to intel_qgv_info as num_qgv_point can be +overwritten in icl_get_qgv_points() +- add gen12_get_dram_info() and simplify gen11_get_dram_info() + +Reviewed-by: Lucas De Marchi +Signed-off-by: José Roberto de Souza +Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-2-jose.souza@intel.com +Signed-off-by: Henning Schild +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_bw.c | 80 +++---------------------------- + drivers/gpu/drm/i915/i915_drv.c | 5 + + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_dram.c | 82 +++++++++++++++++++++++++++++++- + 4 files changed, 93 insertions(+), 75 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_bw.c ++++ b/drivers/gpu/drm/i915/display/intel_bw.c +@@ -20,76 +20,9 @@ struct intel_qgv_point { + struct intel_qgv_info { + struct intel_qgv_point points[I915_NUM_QGV_POINTS]; + u8 num_points; +- u8 num_channels; + u8 t_bl; +- enum intel_dram_type dram_type; + }; + +-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, +- struct intel_qgv_info *qi) +-{ +- u32 val = 0; +- int ret; +- +- ret = sandybridge_pcode_read(dev_priv, +- ICL_PCODE_MEM_SUBSYSYSTEM_INFO | +- ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, +- &val, NULL); +- if (ret) +- return ret; +- +- if (IS_GEN(dev_priv, 12)) { +- switch (val & 0xf) { +- case 0: +- qi->dram_type = INTEL_DRAM_DDR4; +- break; +- case 3: +- qi->dram_type = INTEL_DRAM_LPDDR4; +- break; +- case 4: +- qi->dram_type = INTEL_DRAM_DDR3; +- break; +- case 5: +- qi->dram_type = INTEL_DRAM_LPDDR3; +- break; +- default: +- MISSING_CASE(val & 0xf); +- break; +- } +- } else if (IS_GEN(dev_priv, 11)) { +- switch (val & 0xf) { +- case 0: +- qi->dram_type = INTEL_DRAM_DDR4; +- break; +- case 1: +- qi->dram_type = INTEL_DRAM_DDR3; +- break; +- case 2: +- qi->dram_type = INTEL_DRAM_LPDDR3; +- break; +- case 3: +- qi->dram_type = INTEL_DRAM_LPDDR4; +- break; +- default: +- MISSING_CASE(val & 0xf); +- break; +- } +- } else { +- MISSING_CASE(INTEL_GEN(dev_priv)); +- qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */ +- } +- +- qi->num_channels = (val & 0xf0) >> 4; +- qi->num_points = (val & 0xf00) >> 8; +- +- if (IS_GEN(dev_priv, 12)) +- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; +- else if (IS_GEN(dev_priv, 11)) +- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; +- +- return 0; +-} +- + static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, + int point) +@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, + struct intel_qgv_info *qi) + { ++ const struct dram_info *dram_info = &dev_priv->dram_info; + int i, ret; + +- ret = icl_pcode_read_mem_global_info(dev_priv, qi); +- if (ret) +- return ret; ++ qi->num_points = dram_info->num_qgv_points; ++ ++ if (IS_GEN(dev_priv, 12)) ++ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16; ++ else if (IS_GEN(dev_priv, 11)) ++ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; + + if (drm_WARN_ON(&dev_priv->drm, + qi->num_points > ARRAY_SIZE(qi->points))) +@@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i9 + { + struct intel_qgv_info qi = {}; + bool is_y_tile = true; /* assume y tile may be used */ +- int num_channels; ++ int num_channels = dev_priv->dram_info.num_channels; + int deinterleave; + int ipqdepth, ipqdepthpch; + int dclk_max; +@@ -222,7 +159,6 @@ static int icl_get_bw_info(struct drm_i9 + "Failed to get memory subsystem information, ignoring bandwidth limits"); + return ret; + } +- num_channels = qi.num_channels; + + deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); + dclk_max = icl_sagv_max_dclk(&qi); +--- a/drivers/gpu/drm/i915/i915_drv.c ++++ b/drivers/gpu/drm/i915/i915_drv.c +@@ -609,14 +609,15 @@ static int i915_driver_hw_probe(struct d + goto err_msi; + + intel_opregion_setup(dev_priv); ++ ++ intel_pcode_init(dev_priv); ++ + /* + * Fill the dram structure to get the system raw bandwidth and + * dram info. This will be used for memory latency calculation. + */ + intel_dram_detect(dev_priv); + +- intel_pcode_init(dev_priv); +- + intel_bw_init_hw(dev_priv); + + return 0; +--- a/drivers/gpu/drm/i915/i915_drv.h ++++ b/drivers/gpu/drm/i915/i915_drv.h +@@ -1148,6 +1148,7 @@ struct drm_i915_private { + INTEL_DRAM_LPDDR3, + INTEL_DRAM_LPDDR4 + } type; ++ u8 num_qgv_points; + } dram_info; + + struct intel_bw_info { +--- a/drivers/gpu/drm/i915/intel_dram.c ++++ b/drivers/gpu/drm/i915/intel_dram.c +@@ -5,6 +5,7 @@ + + #include "i915_drv.h" + #include "intel_dram.h" ++#include "intel_sideband.h" + + struct dram_dimm_info { + u8 size, width, ranks; +@@ -433,6 +434,81 @@ static int bxt_get_dram_info(struct drm_ + return 0; + } + ++static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) ++{ ++ struct dram_info *dram_info = &dev_priv->dram_info; ++ u32 val = 0; ++ int ret; ++ ++ ret = sandybridge_pcode_read(dev_priv, ++ ICL_PCODE_MEM_SUBSYSYSTEM_INFO | ++ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, ++ &val, NULL); ++ if (ret) ++ return ret; ++ ++ if (IS_GEN(dev_priv, 12)) { ++ switch (val & 0xf) { ++ case 0: ++ dram_info->type = INTEL_DRAM_DDR4; ++ break; ++ case 3: ++ dram_info->type = INTEL_DRAM_LPDDR4; ++ break; ++ case 4: ++ dram_info->type = INTEL_DRAM_DDR3; ++ break; ++ case 5: ++ dram_info->type = INTEL_DRAM_LPDDR3; ++ break; ++ default: ++ MISSING_CASE(val & 0xf); ++ return -1; ++ } ++ } else { ++ switch (val & 0xf) { ++ case 0: ++ dram_info->type = INTEL_DRAM_DDR4; ++ break; ++ case 1: ++ dram_info->type = INTEL_DRAM_DDR3; ++ break; ++ case 2: ++ dram_info->type = INTEL_DRAM_LPDDR3; ++ break; ++ case 3: ++ dram_info->type = INTEL_DRAM_LPDDR4; ++ break; ++ default: ++ MISSING_CASE(val & 0xf); ++ return -1; ++ } ++ } ++ ++ dram_info->num_channels = (val & 0xf0) >> 4; ++ dram_info->num_qgv_points = (val & 0xf00) >> 8; ++ ++ return 0; ++} ++ ++static int gen11_get_dram_info(struct drm_i915_private *i915) ++{ ++ int ret = skl_get_dram_info(i915); ++ ++ if (ret) ++ return ret; ++ ++ return icl_pcode_read_mem_global_info(i915); ++} ++ ++static int gen12_get_dram_info(struct drm_i915_private *i915) ++{ ++ /* Always needed for GEN12+ */ ++ i915->dram_info.is_16gb_dimm = true; ++ ++ return icl_pcode_read_mem_global_info(i915); ++} ++ + void intel_dram_detect(struct drm_i915_private *i915) + { + struct dram_info *dram_info = &i915->dram_info; +@@ -448,7 +524,11 @@ void intel_dram_detect(struct drm_i915_p + if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915)) + return; + +- if (IS_GEN9_LP(i915)) ++ if (INTEL_GEN(i915) >= 12) ++ ret = gen12_get_dram_info(i915); ++ else if (INTEL_GEN(i915) >= 11) ++ ret = gen11_get_dram_info(i915); ++ else if (IS_GEN9_LP(i915)) + ret = bxt_get_dram_info(i915); + else + ret = skl_get_dram_info(i915); diff --git a/queue-5.10/series b/queue-5.10/series index ee1739914c4..54ec332aabd 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -85,3 +85,5 @@ nilfs2-reject-devices-with-insufficient-block-count.patch media-dvbdev-fix-memleak-in-dvb_register_device.patch media-dvbdev-fix-error-logic-at-dvb_register_device.patch media-dvb-core-fix-use-after-free-due-to-race-at-dvb_register_device.patch +drm-i915-dg1-wait-for-pcode-uncore-handshake-at-startup.patch +drm-i915-gen11-only-load-dram-information-from-pcode.patch