From: Anshuman Khandual Date: Wed, 11 Dec 2024 06:54:25 +0000 (+0530) Subject: docs: arm64: Document EL3 requirements for FEAT_PMUv3 X-Git-Tag: v6.14-rc1~198^2~3^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1e4a5e3679cc4d037982bfc822d939d5ba954e70;p=thirdparty%2Fkernel%2Flinux.git docs: arm64: Document EL3 requirements for FEAT_PMUv3 This documents EL3 requirements for FEAT_PMUv3. The register field MDCR_EL3 .TPM needs to be cleared for accesses into PMU registers without any trap being generated into EL3. PMUv3 registers like PMCCFILTR_EL0, PMCCNTR_EL0 PMCNTENCLR_EL0, PMCNTENSET_EL0, PMCR_EL0, PMEVCNTR_EL0, PMEVTYPER_EL0 etc are already being accessed for perf HW PMU implementation. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Jonathan Corbet Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Link: https://lore.kernel.org/r/20241211065425.1106683-3-anshuman.khandual@arm.com Signed-off-by: Will Deacon --- diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index 1b3ac1394e5f4..cad6fdc96b98b 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -455,6 +455,12 @@ Before jumping into the kernel, the following conditions must be met: - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - For CPUs with FEAT_PMUv3: + + - If EL3 is present: + + - MDCR_EL3.TPM (bit 6) must be initialized to 0b0 + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented