From: Greg Kroah-Hartman Date: Sun, 7 Sep 2025 15:24:05 +0000 (+0200) Subject: 5.15-stable patches X-Git-Tag: v5.4.299~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1e8c014704a17ef35c7b317e4a71edf41ebdd0e2;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: clk-qcom-gdsc-set-retain_ff-before-moving-to-hw-ctrl.patch --- diff --git a/queue-5.15/clk-qcom-gdsc-set-retain_ff-before-moving-to-hw-ctrl.patch b/queue-5.15/clk-qcom-gdsc-set-retain_ff-before-moving-to-hw-ctrl.patch new file mode 100644 index 0000000000..033d221d65 --- /dev/null +++ b/queue-5.15/clk-qcom-gdsc-set-retain_ff-before-moving-to-hw-ctrl.patch @@ -0,0 +1,84 @@ +From stable+bounces-178044-greg=kroah.com@vger.kernel.org Sun Sep 7 16:57:23 2025 +From: Sasha Levin +Date: Sun, 7 Sep 2025 10:57:15 -0400 +Subject: clk: qcom: gdsc: Set retain_ff before moving to HW CTRL +To: stable@vger.kernel.org +Cc: Taniya Das , Imran Shaik , Bjorn Andersson , Sasha Levin +Message-ID: <20250907145715.636498-1-sashal@kernel.org> + +From: Taniya Das + +[ Upstream commit 25708f73ff171bb4171950c9f4be5aa8504b8459 ] + +Enable the retain_ff_enable bit of GDSCR only if the GDSC is already ON. +Once the GDSCR moves to HW control, SW no longer can determine the state +of the GDSCR and setting the retain_ff bit could destroy all the register +contents we intended to save. +Therefore, move the retain_ff configuration before switching the GDSC to +HW trigger mode. + +Cc: stable@vger.kernel.org +Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") +Signed-off-by: Taniya Das +Reviewed-by: Imran Shaik +Tested-by: Imran Shaik # on QCS8300 +Link: https://lore.kernel.org/r/20250214-gdsc_fixes-v1-1-73e56d68a80f@quicinc.com +Signed-off-by: Bjorn Andersson +[ Changed error path ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gdsc.c | 21 +++++++++++---------- + 1 file changed, 11 insertions(+), 10 deletions(-) + +--- a/drivers/clk/qcom/gdsc.c ++++ b/drivers/clk/qcom/gdsc.c +@@ -273,6 +273,9 @@ static int gdsc_enable(struct generic_pm + */ + udelay(1); + ++ if (sc->flags & RETAIN_FF_ENABLE) ++ gdsc_retain_ff_on(sc); ++ + /* Turn on HW trigger mode if supported */ + if (sc->flags & HW_CTRL) { + ret = gdsc_hwctrl(sc, true); +@@ -289,9 +292,6 @@ static int gdsc_enable(struct generic_pm + udelay(1); + } + +- if (sc->flags & RETAIN_FF_ENABLE) +- gdsc_retain_ff_on(sc); +- + return 0; + } + +@@ -392,13 +392,6 @@ static int gdsc_init(struct gdsc *sc) + return ret; + } + +- /* Turn on HW trigger mode if supported */ +- if (sc->flags & HW_CTRL) { +- ret = gdsc_hwctrl(sc, true); +- if (ret < 0) +- return ret; +- } +- + /* + * Make sure the retain bit is set if the GDSC is already on, + * otherwise we end up turning off the GDSC and destroying all +@@ -406,6 +399,14 @@ static int gdsc_init(struct gdsc *sc) + */ + if (sc->flags & RETAIN_FF_ENABLE) + gdsc_retain_ff_on(sc); ++ ++ /* Turn on HW trigger mode if supported */ ++ if (sc->flags & HW_CTRL) { ++ ret = gdsc_hwctrl(sc, true); ++ if (ret < 0) ++ return ret; ++ } ++ + } else if (sc->flags & ALWAYS_ON) { + /* If ALWAYS_ON GDSCs are not ON, turn them ON */ + gdsc_enable(&sc->pd); diff --git a/queue-5.15/series b/queue-5.15/series index d852f39cb3..e4d504168e 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -59,3 +59,4 @@ spi-spi-fsl-lpspi-set-correct-chip-select-polarity-b.patch spi-spi-fsl-lpspi-reset-fifo-and-disable-module-on-t.patch drm-bridge-ti-sn65dsi86-fix-refclk-setting.patch perf-bpf-event-fix-use-after-free-in-synthesis.patch +clk-qcom-gdsc-set-retain_ff-before-moving-to-hw-ctrl.patch