From: Christoph Hellwig Date: Wed, 8 Apr 2020 15:27:42 +0000 (+0200) Subject: x86/mm: Add a x86_has_pat_wp() helper X-Git-Tag: v5.8-rc1~134^2~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1f6f655e01adebf5bd5e6c3da2e843c104ded051;p=thirdparty%2Fkernel%2Flinux.git x86/mm: Add a x86_has_pat_wp() helper Abstract the ioremap code away from the caching mode internals. Signed-off-by: Christoph Hellwig Signed-off-by: Borislav Petkov Acked-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20200408152745.1565832-2-hch@lst.de --- diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h index 9c2447b3555dc..1e4e99b407110 100644 --- a/arch/x86/include/asm/memtype.h +++ b/arch/x86/include/asm/memtype.h @@ -24,4 +24,6 @@ extern void memtype_free_io(resource_size_t start, resource_size_t end); extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn); +bool x86_has_pat_wp(void); + #endif /* _ASM_X86_MEMTYPE_H */ diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 1bba16c5742b3..6005f83b81111 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -71,6 +71,12 @@ uint8_t __pte2cachemode_tbl[8] = { }; EXPORT_SYMBOL(__pte2cachemode_tbl); +/* Check that the write-protect PAT entry is set for write-protect */ +bool x86_has_pat_wp(void) +{ + return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP; +} + static unsigned long __initdata pgt_buf_start; static unsigned long __initdata pgt_buf_end; static unsigned long __initdata pgt_buf_top; diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 18c637c0dc6fa..41536f523a5ff 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -778,10 +778,8 @@ void __init *early_memremap_encrypted(resource_size_t phys_addr, void __init *early_memremap_encrypted_wp(resource_size_t phys_addr, unsigned long size) { - /* Be sure the write-protect PAT entry is set for write-protect */ - if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP) + if (!x86_has_pat_wp()) return NULL; - return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_ENC_WP); } @@ -799,10 +797,8 @@ void __init *early_memremap_decrypted(resource_size_t phys_addr, void __init *early_memremap_decrypted_wp(resource_size_t phys_addr, unsigned long size) { - /* Be sure the write-protect PAT entry is set for write-protect */ - if (__pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] != _PAGE_CACHE_MODE_WP) + if (!x86_has_pat_wp()) return NULL; - return early_memremap_prot(phys_addr, size, __PAGE_KERNEL_NOENC_WP); } #endif /* CONFIG_AMD_MEM_ENCRYPT */