From: Catalin Marinas Date: Fri, 22 Dec 2017 17:40:58 +0000 (+0000) Subject: Merge branch 'for-next/52-bit-pa' into for-next/core X-Git-Tag: v4.16-rc1~160^2~69 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1f911c3a1140e1668e68791fb6dd07757e2f3956;p=thirdparty%2Fkernel%2Flinux.git Merge branch 'for-next/52-bit-pa' into for-next/core * for-next/52-bit-pa: arm64: enable 52-bit physical address support arm64: allow ID map to be extended to 52 bits arm64: handle 52-bit physical addresses in page table entries arm64: don't open code page table entry creation arm64: head.S: handle 52-bit PAs in PTEs in early page table setup arm64: handle 52-bit addresses in TTBR arm64: limit PA size to supported range arm64: add kconfig symbol to configure physical address size --- 1f911c3a1140e1668e68791fb6dd07757e2f3956 diff --cc arch/arm64/include/asm/pgtable-hwdef.h index 8df4cb6ac6f71,85069f37ae37e..e1f6679d763ea --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@@ -272,7 -282,8 +282,9 @@@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) + #define TCR_IPS_SHIFT 32 + #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --cc arch/arm64/mm/proc.S index 3146dc96f05b3,e79db5a7576a5..bc334588f2345 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@@ -138,14 -138,13 +138,15 @@@ ENDPROC(cpu_do_resume * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) - phys_to_ttbr x0, x2 - pre_ttbr0_update_workaround x2, x3, x4 + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id bfi x2, x1, #48, #16 // set the ASID - msr ttbr0_el1, x2 // set TTBR0 + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + isb - msr ttbr0_el1, x0 // now update TTBR0 ++ phys_to_ttbr x0, x2 ++ msr ttbr0_el1, x2 // now update TTBR0 isb - post_ttbr0_update_workaround + post_ttbr_update_workaround ret ENDPROC(cpu_do_switch_mm)