From: Greg Kroah-Hartman Date: Wed, 18 Feb 2009 17:32:59 +0000 (-0800) Subject: .28 patches X-Git-Tag: v2.6.27.19~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=1fb958bad05b06398e6db8c0f3999f5224147df3;p=thirdparty%2Fkernel%2Fstable-queue.git .28 patches --- diff --git a/queue-2.6.28/fix-intel-iommu-write-buffer-flushing.patch b/queue-2.6.28/fix-intel-iommu-write-buffer-flushing.patch new file mode 100644 index 00000000000..f1f4701264b --- /dev/null +++ b/queue-2.6.28/fix-intel-iommu-write-buffer-flushing.patch @@ -0,0 +1,64 @@ +From ca77fde8e62cecb2c0769052228d15b901367af8 Mon Sep 17 00:00:00 2001 +From: David Woodhouse +Date: Fri, 13 Feb 2009 23:18:03 +0000 +Subject: Fix Intel IOMMU write-buffer flushing + +From: David Woodhouse + +commit ca77fde8e62cecb2c0769052228d15b901367af8 upstream. + +This is the cause of the DMA faults and disk corruption that people have +been seeing. Some chipsets neglect to report the RWBF "capability" -- +the flag which says that we need to flush the chipset write-buffer when +changing the DMA page tables, to ensure that the change is visible to +the IOMMU. + +Override that bit on the affected chipsets, and everything is happy +again. + +Thanks to Chris and Bhavesh and others for helping to debug. + +Signed-off-by: David Woodhouse +Tested-by: Chris Wright +Reviewed-by: Bhavesh Davda +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/intel-iommu.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/drivers/pci/intel-iommu.c ++++ b/drivers/pci/intel-iommu.c +@@ -506,7 +506,7 @@ static void iommu_flush_write_buffer(str + u32 val; + unsigned long flag; + +- if (!cap_rwbf(iommu->cap)) ++ if (!rwbf_quirk && !cap_rwbf(iommu->cap)) + return; + val = iommu->gcmd | DMA_GCMD_WBF; + +@@ -1315,6 +1315,8 @@ static void domain_remove_dev_info(struc + spin_unlock_irqrestore(&device_domain_lock, flags); + } + ++static int rwbf_quirk = 0; ++ + /* + * find_domain + * Note: we use struct pci_dev->dev.archdata.iommu stores the info +@@ -2436,3 +2438,13 @@ u64 intel_iommu_iova_to_pfn(struct dmar_ + return pfn >> VTD_PAGE_SHIFT; + } + EXPORT_SYMBOL_GPL(intel_iommu_iova_to_pfn); ++ ++static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) ++{ ++ /* Mobile 4 Series Chipset neglects to set RWBF capability, ++ but needs it */ ++ printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); ++ rwbf_quirk = 1; ++} ++ ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); diff --git a/queue-2.6.28/powerpc-vsx-fix-vsx-alignment-handler-for-regs-32-63.patch b/queue-2.6.28/powerpc-vsx-fix-vsx-alignment-handler-for-regs-32-63.patch new file mode 100644 index 00000000000..72e7ca3b5e8 --- /dev/null +++ b/queue-2.6.28/powerpc-vsx-fix-vsx-alignment-handler-for-regs-32-63.patch @@ -0,0 +1,40 @@ +From 26456dcfb8d8e43b1b64b2a14710694cf7a72f05 Mon Sep 17 00:00:00 2001 +From: Michael Neuling +Date: Thu, 12 Feb 2009 19:08:58 +0000 +Subject: powerpc/vsx: Fix VSX alignment handler for regs 32-63 + +From: Michael Neuling + +commit 26456dcfb8d8e43b1b64b2a14710694cf7a72f05 upstream. + +Fix the VSX alignment handler for VSX registers > 32. 32-63 are stored +in the VMX part of the thread_struct not the FPR part. + +Signed-off-by: Michael Neuling +Signed-off-by: Benjamin Herrenschmidt +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/kernel/align.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/arch/powerpc/kernel/align.c ++++ b/arch/powerpc/kernel/align.c +@@ -646,11 +646,16 @@ static int emulate_vsx(unsigned char __u + unsigned int areg, struct pt_regs *regs, + unsigned int flags, unsigned int length) + { +- char *ptr = (char *) ¤t->thread.TS_FPR(reg); ++ char *ptr; + int ret = 0; + + flush_vsx_to_thread(current); + ++ if (reg < 32) ++ ptr = (char *) ¤t->thread.TS_FPR(reg); ++ else ++ ptr = (char *) ¤t->thread.vr[reg - 32]; ++ + if (flags & ST) + ret = __copy_to_user(addr, ptr, length); + else { diff --git a/queue-2.6.28/sata_nv-give-up-hardreset-on-nf2.patch b/queue-2.6.28/sata_nv-give-up-hardreset-on-nf2.patch new file mode 100644 index 00000000000..68bd1aea615 --- /dev/null +++ b/queue-2.6.28/sata_nv-give-up-hardreset-on-nf2.patch @@ -0,0 +1,52 @@ +From 7dac745b8e367c99175b8f0d014d996f0e5ed9e5 Mon Sep 17 00:00:00 2001 +From: Tejun Heo +Date: Thu, 12 Feb 2009 10:34:32 +0900 +Subject: sata_nv: give up hardreset on nf2 + +From: Tejun Heo + +commit 7dac745b8e367c99175b8f0d014d996f0e5ed9e5 upstream. + +Kernel bz#12176 reports that nf2 hardreset simply doesn't work. Give +up. Argh... + +Signed-off-by: Tejun Heo +Cc: Robert Hancock +Reported-by: Saro +Signed-off-by: Jeff Garzik +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/ata/sata_nv.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/ata/sata_nv.c ++++ b/drivers/ata/sata_nv.c +@@ -421,19 +421,21 @@ static struct ata_port_operations nv_gen + .hardreset = ATA_OP_NULL, + }; + +-/* OSDL bz3352 reports that nf2/3 controllers can't determine device +- * signature reliably. Also, the following thread reports detection +- * failure on cold boot with the standard debouncing timing. ++/* nf2 is ripe with hardreset related problems. ++ * ++ * kernel bz#3352 reports nf2/3 controllers can't determine device ++ * signature reliably. The following thread reports detection failure ++ * on cold boot with the standard debouncing timing. + * + * http://thread.gmane.org/gmane.linux.ide/34098 + * +- * Debounce with hotplug timing and request follow-up SRST. ++ * And bz#12176 reports that hardreset simply doesn't work on nf2. ++ * Give up on it and just don't do hardreset. + */ + static struct ata_port_operations nv_nf2_ops = { +- .inherits = &nv_common_ops, ++ .inherits = &nv_generic_ops, + .freeze = nv_nf2_freeze, + .thaw = nv_nf2_thaw, +- .hardreset = nv_noclassify_hardreset, + }; + + /* For initial probing after boot and hot plugging, hardreset mostly diff --git a/queue-2.6.28/series b/queue-2.6.28/series index 688f5c0ea4f..99790116741 100644 --- a/queue-2.6.28/series +++ b/queue-2.6.28/series @@ -1,2 +1,6 @@ pid-implement-ns_of_pid.patch mqueue-fix-si_pid-value-in-mqueue-do_notify.patch +watchdog-itco_wdt-fix-smi_en-regression-2.patch +powerpc-vsx-fix-vsx-alignment-handler-for-regs-32-63.patch +sata_nv-give-up-hardreset-on-nf2.patch +fix-intel-iommu-write-buffer-flushing.patch diff --git a/queue-2.6.28/watchdog-itco_wdt-fix-smi_en-regression-2.patch b/queue-2.6.28/watchdog-itco_wdt-fix-smi_en-regression-2.patch new file mode 100644 index 00000000000..e67e3f21cd5 --- /dev/null +++ b/queue-2.6.28/watchdog-itco_wdt-fix-smi_en-regression-2.patch @@ -0,0 +1,205 @@ +From 12d60e28bed3f593aac5385acbdbb089eb8ae21e Mon Sep 17 00:00:00 2001 +From: Wim Van Sebroeck +Date: Wed, 28 Jan 2009 20:51:04 +0000 +Subject: WATCHDOG: iTCO_wdt: fix SMI_EN regression 2 + +From: Wim Van Sebroeck + +commit 12d60e28bed3f593aac5385acbdbb089eb8ae21e upstream. + +bugzilla: #12363 +commit 7cd5b08be3c489df11b559fef210b81133764ad4 added a second regression: +some Dell's and Compaq's lockup on boot. So we revert most of the code. +The ICH9 reboot issue remains in place and will need some more fixing... :-( + +Signed-off-by: Wim Van Sebroeck +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/watchdog/Kconfig | 2 - + drivers/watchdog/iTCO_vendor_support.c | 32 ++++++++++++++++++++++++++---- + drivers/watchdog/iTCO_wdt.c | 35 +++++++++++++-------------------- + 3 files changed, 43 insertions(+), 26 deletions(-) + +--- a/drivers/watchdog/iTCO_vendor_support.c ++++ b/drivers/watchdog/iTCO_vendor_support.c +@@ -1,7 +1,7 @@ + /* + * intel TCO vendor specific watchdog driver support + * +- * (c) Copyright 2006-2008 Wim Van Sebroeck . ++ * (c) Copyright 2006-2009 Wim Van Sebroeck . + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License +@@ -19,7 +19,7 @@ + + /* Module and version information */ + #define DRV_NAME "iTCO_vendor_support" +-#define DRV_VERSION "1.02" ++#define DRV_VERSION "1.03" + #define PFX DRV_NAME ": " + + /* Includes */ +@@ -77,6 +77,26 @@ MODULE_PARM_DESC(vendorsupport, "iTCO ve + * 20.6 seconds. + */ + ++static void supermicro_old_pre_start(unsigned long acpibase) ++{ ++ unsigned long val32; ++ ++ /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ ++ val32 = inl(SMI_EN); ++ val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ ++ outl(val32, SMI_EN); /* Needed to activate watchdog */ ++} ++ ++static void supermicro_old_pre_stop(unsigned long acpibase) ++{ ++ unsigned long val32; ++ ++ /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ ++ val32 = inl(SMI_EN); ++ val32 |= 0x00002000; /* Turn on SMI clearing watchdog */ ++ outl(val32, SMI_EN); /* Needed to deactivate watchdog */ ++} ++ + static void supermicro_old_pre_keepalive(unsigned long acpibase) + { + /* Reload TCO Timer (done in iTCO_wdt_keepalive) + */ +@@ -228,14 +248,18 @@ static void supermicro_new_pre_set_heart + void iTCO_vendor_pre_start(unsigned long acpibase, + unsigned int heartbeat) + { +- if (vendorsupport == SUPERMICRO_NEW_BOARD) ++ if (vendorsupport == SUPERMICRO_OLD_BOARD) ++ supermicro_old_pre_start(acpibase); ++ else if (vendorsupport == SUPERMICRO_NEW_BOARD) + supermicro_new_pre_start(heartbeat); + } + EXPORT_SYMBOL(iTCO_vendor_pre_start); + + void iTCO_vendor_pre_stop(unsigned long acpibase) + { +- if (vendorsupport == SUPERMICRO_NEW_BOARD) ++ if (vendorsupport == SUPERMICRO_OLD_BOARD) ++ supermicro_old_pre_stop(acpibase); ++ else if (vendorsupport == SUPERMICRO_NEW_BOARD) + supermicro_new_pre_stop(); + } + EXPORT_SYMBOL(iTCO_vendor_pre_stop); +--- a/drivers/watchdog/iTCO_wdt.c ++++ b/drivers/watchdog/iTCO_wdt.c +@@ -1,7 +1,7 @@ + /* +- * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets) ++ * intel TCO Watchdog Driver (Used in i82801 and i63xxESB chipsets) + * +- * (c) Copyright 2006-2008 Wim Van Sebroeck . ++ * (c) Copyright 2006-2009 Wim Van Sebroeck . + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License +@@ -63,7 +63,7 @@ + + /* Module and version information */ + #define DRV_NAME "iTCO_wdt" +-#define DRV_VERSION "1.04" ++#define DRV_VERSION "1.05" + #define PFX DRV_NAME ": " + + /* Includes */ +@@ -236,16 +236,16 @@ MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tb + + /* Address definitions for the TCO */ + /* TCO base address */ +-#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 ++#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 + /* SMI Control and Enable Register */ +-#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 ++#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 + + #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */ + #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ +-#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ +-#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ +-#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ +-#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */ ++#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ ++#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ ++#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ ++#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */ + #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */ + #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */ + #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */ +@@ -338,7 +338,6 @@ static int iTCO_wdt_unset_NO_REBOOT_bit( + static int iTCO_wdt_start(void) + { + unsigned int val; +- unsigned long val32; + + spin_lock(&iTCO_wdt_private.io_lock); + +@@ -351,11 +350,6 @@ static int iTCO_wdt_start(void) + return -EIO; + } + +- /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ +- val32 = inl(SMI_EN); +- val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ +- outl(val32, SMI_EN); +- + /* Force the timer to its reload value by writing to the TCO_RLD + register */ + if (iTCO_wdt_private.iTCO_version == 2) +@@ -378,7 +372,6 @@ static int iTCO_wdt_start(void) + static int iTCO_wdt_stop(void) + { + unsigned int val; +- unsigned long val32; + + spin_lock(&iTCO_wdt_private.io_lock); + +@@ -390,11 +383,6 @@ static int iTCO_wdt_stop(void) + outw(val, TCO1_CNT); + val = inw(TCO1_CNT); + +- /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ +- val32 = inl(SMI_EN); +- val32 |= 0x00002000; +- outl(val32, SMI_EN); +- + /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ + iTCO_wdt_set_NO_REBOOT_bit(); + +@@ -649,6 +637,7 @@ static int __devinit iTCO_wdt_init(struc + int ret; + u32 base_address; + unsigned long RCBA; ++ unsigned long val32; + + /* + * Find the ACPI/PM base I/O address which is the base +@@ -695,6 +684,10 @@ static int __devinit iTCO_wdt_init(struc + ret = -EIO; + goto out; + } ++ /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ ++ val32 = inl(SMI_EN); ++ val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ ++ outl(val32, SMI_EN); + + /* The TCO I/O registers reside in a 32-byte range pointed to + by the TCOBASE value */ +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -399,7 +399,7 @@ config ITCO_WDT + ---help--- + Hardware driver for the intel TCO timer based watchdog devices. + These drivers are included in the Intel 82801 I/O Controller +- Hub family (from ICH0 up to ICH8) and in the Intel 6300ESB ++ Hub family (from ICH0 up to ICH10) and in the Intel 63xxESB + controller hub. + + The TCO (Total Cost of Ownership) timer is a watchdog timer