From: Neil Armstrong Date: Wed, 5 Oct 2016 13:53:50 +0000 (+0200) Subject: ARM64: dts: meson-gx: Add missing L2 cache node X-Git-Tag: v4.10-rc1~81^2~14^2~21 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=214ec5230d216763d0448c6a747a50cef64bcff6;p=thirdparty%2Flinux.git ARM64: dts: meson-gx: Add missing L2 cache node In order to remove the boot warning : [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 And add missing L2 cache hierarchy information, add a simple l2 cache node and reference it from the A53 cpu nodes. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 0737056b369f1..a6cd953ef7e17 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -64,6 +64,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -71,6 +72,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -78,6 +80,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -85,6 +88,11 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; }; };