From: Greg Kroah-Hartman Date: Sun, 20 May 2018 07:56:30 +0000 (+0200) Subject: 4.16-stable patches X-Git-Tag: v4.9.102~31 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2175f9dfae14214c0c38738574b494a1b5b0a628;p=thirdparty%2Fkernel%2Fstable-queue.git 4.16-stable patches added patches: arm64-dts-marvell-armada-cp110-add-clocks-for-the-xmdio-node.patch arm64-dts-marvell-armada-cp110-add-mg_core_clk-for-ethernet-node.patch i2c-designware-fix-poll-after-enable-regression.patch mtd-rawnand-marvell-fix-read-logic-for-layouts-with-nchunks-2.patch powerpc-powernv-fix-nvram-sleep-in-invalid-context-when-crashing.patch --- diff --git a/queue-4.16/arm64-dts-marvell-armada-cp110-add-clocks-for-the-xmdio-node.patch b/queue-4.16/arm64-dts-marvell-armada-cp110-add-clocks-for-the-xmdio-node.patch new file mode 100644 index 00000000000..cdd2a8f516a --- /dev/null +++ b/queue-4.16/arm64-dts-marvell-armada-cp110-add-clocks-for-the-xmdio-node.patch @@ -0,0 +1,40 @@ +From a057344806d035cb9ac991619fa07854e807562d Mon Sep 17 00:00:00 2001 +From: Maxime Chevallier +Date: Wed, 25 Apr 2018 13:07:31 +0200 +Subject: ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node + +From: Maxime Chevallier + +commit a057344806d035cb9ac991619fa07854e807562d upstream. + +The Marvell XSMI controller needs 3 clocks to operate correctly : + - The MG clock (clk 5) + - The MG Core clock (clk 6) + - The GOP clock (clk 18) + + This commit adds them, to avoid system hangs when using these + interfaces. + +[gregory.clement: use the real first commit to fix and add the cc:stable +flag] +Fixes: f66b2aff46ea ("arm64: dts: marvell: add xmdio nodes for 7k/8k") +Cc: +Signed-off-by: Maxime Chevallier +Signed-off-by: Gregory CLEMENT +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +@@ -143,6 +143,8 @@ + #size-cells = <0>; + compatible = "marvell,xmdio"; + reg = <0x12a600 0x10>; ++ clocks = <&CP110_LABEL(clk) 1 5>, ++ <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; + status = "disabled"; + }; + diff --git a/queue-4.16/arm64-dts-marvell-armada-cp110-add-mg_core_clk-for-ethernet-node.patch b/queue-4.16/arm64-dts-marvell-armada-cp110-add-mg_core_clk-for-ethernet-node.patch new file mode 100644 index 00000000000..ca838fe4438 --- /dev/null +++ b/queue-4.16/arm64-dts-marvell-armada-cp110-add-mg_core_clk-for-ethernet-node.patch @@ -0,0 +1,70 @@ +From f43194c1447c9536efb0859c2f3f46f6bf2b9154 Mon Sep 17 00:00:00 2001 +From: Maxime Chevallier +Date: Wed, 25 Apr 2018 20:19:47 +0200 +Subject: ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node + +From: Maxime Chevallier + +commit f43194c1447c9536efb0859c2f3f46f6bf2b9154 upstream. + +Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk" +clock to avoid system hangs when powering some network interfaces up. + +This issue appeared after a recent clock rework on Armada 7K/8K platforms. + +This commit adds the new clock and updates the documentation accordingly. + +[gregory.clement: use the real first commit to fix and add the cc:stable +flag] +Fixes: e3af9f7c6ece ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node") +Cc: +Signed-off-by: Maxime Chevallier +Signed-off-by: Gregory CLEMENT +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/net/marvell-pp2.txt | 9 +++++---- + arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 5 +++-- + 2 files changed, 8 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt ++++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt +@@ -21,9 +21,10 @@ Required properties: + - main controller clock (for both armada-375-pp2 and armada-7k-pp2) + - GOP clock (for both armada-375-pp2 and armada-7k-pp2) + - MG clock (only for armada-7k-pp2) ++ - MG Core clock (only for armada-7k-pp2) + - AXI clock (only for armada-7k-pp2) +-- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk" +- and "axi_clk" (the 2 latter only for armada-7k-pp2). ++- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk", ++ "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2). + + The ethernet ports are represented by subnodes. At least one port is + required. +@@ -80,8 +81,8 @@ cpm_ethernet: ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, +- <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>; +- clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk"; ++ <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>; ++ clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk"; + + eth0: eth0 { + interrupts = , +--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi ++++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +@@ -40,9 +40,10 @@ + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, +- <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>; ++ <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, ++ <&CP110_LABEL(clk) 1 18>; + clock-names = "pp_clk", "gop_clk", +- "mg_clk", "axi_clk"; ++ "mg_clk", "mg_core_clk", "axi_clk"; + marvell,system-controller = <&CP110_LABEL(syscon0)>; + status = "disabled"; + dma-coherent; diff --git a/queue-4.16/i2c-designware-fix-poll-after-enable-regression.patch b/queue-4.16/i2c-designware-fix-poll-after-enable-regression.patch new file mode 100644 index 00000000000..2e72066be20 --- /dev/null +++ b/queue-4.16/i2c-designware-fix-poll-after-enable-regression.patch @@ -0,0 +1,43 @@ +From 06cb616b1bca7080824acfedb3d4c898e7a64836 Mon Sep 17 00:00:00 2001 +From: Alexander Monakov +Date: Sat, 28 Apr 2018 16:56:06 +0300 +Subject: i2c: designware: fix poll-after-enable regression + +From: Alexander Monakov + +commit 06cb616b1bca7080824acfedb3d4c898e7a64836 upstream. + +Not all revisions of DW I2C controller implement the enable status register. +On platforms where that's the case (e.g. BG2CD and SPEAr ARM SoCs), waiting +for enable will time out as reading the unimplemented register yields zero. + +It was observed that reading the IC_ENABLE_STATUS register once suffices to +avoid getting it stuck on Bay Trail hardware, so replace polling with one +dummy read of the register. + +Fixes: fba4adbbf670 ("i2c: designware: must wait for enable") +Signed-off-by: Alexander Monakov +Tested-by: Ben Gardner +Acked-by: Jarkko Nikula +Signed-off-by: Wolfram Sang +Cc: stable@kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/i2c/busses/i2c-designware-master.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/i2c/busses/i2c-designware-master.c ++++ b/drivers/i2c/busses/i2c-designware-master.c +@@ -209,7 +209,10 @@ static void i2c_dw_xfer_init(struct dw_i + i2c_dw_disable_int(dev); + + /* Enable the adapter */ +- __i2c_dw_enable_and_wait(dev, true); ++ __i2c_dw_enable(dev, true); ++ ++ /* Dummy read to avoid the register getting stuck on Bay Trail */ ++ dw_readl(dev, DW_IC_ENABLE_STATUS); + + /* Clear and enable interrupts */ + dw_readl(dev, DW_IC_CLR_INTR); diff --git a/queue-4.16/mtd-rawnand-marvell-fix-read-logic-for-layouts-with-nchunks-2.patch b/queue-4.16/mtd-rawnand-marvell-fix-read-logic-for-layouts-with-nchunks-2.patch new file mode 100644 index 00000000000..9990f7d630d --- /dev/null +++ b/queue-4.16/mtd-rawnand-marvell-fix-read-logic-for-layouts-with-nchunks-2.patch @@ -0,0 +1,52 @@ +From 90d617633368ab97a2c7571c6e66dad54f39228d Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Wed, 9 May 2018 09:13:58 +0200 +Subject: mtd: rawnand: marvell: Fix read logic for layouts with ->nchunks > 2 + +From: Boris Brezillon + +commit 90d617633368ab97a2c7571c6e66dad54f39228d upstream. + +The code is doing monolithic reads for all chunks except the last one +which is wrong since a monolithic read will issue the +READ0+ADDRS+READ_START sequence. It not only takes longer because it +forces the NAND chip to reload the page content into its internal +cache, but by doing that we also reset the column pointer to 0, which +means we'll always read the first chunk instead of moving to the next +one. + +Rework the code to do a monolithic read only for the first chunk, +then switch to naked reads for all intermediate chunks and finally +issue a last naked read for the last chunk. + +Fixes: 02f26ecf8c77 mtd: nand: add reworked Marvell NAND controller driver +Cc: stable@vger.kernel.org +Reported-by: Chris Packham +Signed-off-by: Boris Brezillon +Tested-by: Chris Packham +Acked-by: Miquel Raynal +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/nand/marvell_nand.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/marvell_nand.c ++++ b/drivers/mtd/nand/marvell_nand.c +@@ -1190,11 +1190,13 @@ static void marvell_nfc_hw_ecc_bch_read_ + NDCB0_CMD2(NAND_CMD_READSTART); + + /* +- * Trigger the naked read operation only on the last chunk. +- * Otherwise, use monolithic read. ++ * Trigger the monolithic read on the first chunk, then naked read on ++ * intermediate chunks and finally a last naked read on the last chunk. + */ +- if (lt->nchunks == 1 || (chunk < lt->nchunks - 1)) ++ if (chunk == 0) + nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); ++ else if (chunk < lt->nchunks - 1) ++ nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); + else + nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); + diff --git a/queue-4.16/powerpc-powernv-fix-nvram-sleep-in-invalid-context-when-crashing.patch b/queue-4.16/powerpc-powernv-fix-nvram-sleep-in-invalid-context-when-crashing.patch new file mode 100644 index 00000000000..caaba25f780 --- /dev/null +++ b/queue-4.16/powerpc-powernv-fix-nvram-sleep-in-invalid-context-when-crashing.patch @@ -0,0 +1,55 @@ +From c1d2a31397ec51f0370f6bd17b19b39152c263cb Mon Sep 17 00:00:00 2001 +From: Nicholas Piggin +Date: Tue, 15 May 2018 01:59:47 +1000 +Subject: powerpc/powernv: Fix NVRAM sleep in invalid context when crashing + +From: Nicholas Piggin + +commit c1d2a31397ec51f0370f6bd17b19b39152c263cb upstream. + +Similarly to opal_event_shutdown, opal_nvram_write can be called in +the crash path with irqs disabled. Special case the delay to avoid +sleeping in invalid context. + +Fixes: 3b8070335f75 ("powerpc/powernv: Fix OPAL NVRAM driver OPAL_BUSY loops") +Cc: stable@vger.kernel.org # v3.2 +Signed-off-by: Nicholas Piggin +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/platforms/powernv/opal-nvram.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/powerpc/platforms/powernv/opal-nvram.c ++++ b/arch/powerpc/platforms/powernv/opal-nvram.c +@@ -44,6 +44,10 @@ static ssize_t opal_nvram_read(char *buf + return count; + } + ++/* ++ * This can be called in the panic path with interrupts off, so use ++ * mdelay in that case. ++ */ + static ssize_t opal_nvram_write(char *buf, size_t count, loff_t *index) + { + s64 rc = OPAL_BUSY; +@@ -58,10 +62,16 @@ static ssize_t opal_nvram_write(char *bu + while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { + rc = opal_write_nvram(__pa(buf), count, off); + if (rc == OPAL_BUSY_EVENT) { +- msleep(OPAL_BUSY_DELAY_MS); ++ if (in_interrupt() || irqs_disabled()) ++ mdelay(OPAL_BUSY_DELAY_MS); ++ else ++ msleep(OPAL_BUSY_DELAY_MS); + opal_poll_events(NULL); + } else if (rc == OPAL_BUSY) { +- msleep(OPAL_BUSY_DELAY_MS); ++ if (in_interrupt() || irqs_disabled()) ++ mdelay(OPAL_BUSY_DELAY_MS); ++ else ++ msleep(OPAL_BUSY_DELAY_MS); + } + } + diff --git a/queue-4.16/series b/queue-4.16/series index 5f9c332b7ed..9da9bd922e6 100644 --- a/queue-4.16/series +++ b/queue-4.16/series @@ -26,3 +26,8 @@ tee-shm-fix-use-after-free-via-temporarily-dropped-reference.patch netfilter-nf_tables-free-set-name-in-error-path.patch netfilter-nf_tables-can-t-fail-after-linking-rule-into-active-rule-list.patch netfilter-nf_tables-nf_tables_obj_lookup_byhandle-can-be-static.patch +arm64-dts-marvell-armada-cp110-add-clocks-for-the-xmdio-node.patch +arm64-dts-marvell-armada-cp110-add-mg_core_clk-for-ethernet-node.patch +i2c-designware-fix-poll-after-enable-regression.patch +mtd-rawnand-marvell-fix-read-logic-for-layouts-with-nchunks-2.patch +powerpc-powernv-fix-nvram-sleep-in-invalid-context-when-crashing.patch