From: Ju-Zhe Zhong Date: Mon, 6 Feb 2023 05:20:30 +0000 (+0800) Subject: RISC-V: Add vzext.vf8 C++ API tests X-Git-Tag: basepoints/gcc-14~1354 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=221f26c9624586b5cec6c5bb8c0a63e21359d1f6;p=thirdparty%2Fgcc.git RISC-V: Add vzext.vf8 C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vzext_vf8-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf8-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf8-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_mu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_mu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_mu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tum-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tum-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tum-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C new file mode 100644 index 000000000000..caf23bc78d9b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C new file mode 100644 index 000000000000..b021b28e02b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C new file mode 100644 index 000000000000..8904ac4ed9d4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf8(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C new file mode 100644 index 000000000000..5d96491e1436 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C new file mode 100644 index 000000000000..c4d24b85ab35 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C new file mode 100644 index 000000000000..74bd3ca29f1e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C new file mode 100644 index 000000000000..f782835241b4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C new file mode 100644 index 000000000000..9ca40128b4f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C new file mode 100644 index 000000000000..5b8c5e448bed --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C new file mode 100644 index 000000000000..b7538f15a498 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C new file mode 100644 index 000000000000..10869ac00051 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C new file mode 100644 index 000000000000..e67a477d900b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C new file mode 100644 index 000000000000..78d14a465e64 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C new file mode 100644 index 000000000000..900920f9f0b4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C new file mode 100644 index 000000000000..f8efb69dff0c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */