From: Sasha Levin Date: Mon, 15 May 2023 01:42:07 +0000 (-0400) Subject: Fixes for 6.2 X-Git-Tag: v4.14.315~58 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=237d6508e224fdcaf611d4a589d522ea8f713541;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.2 Signed-off-by: Sasha Levin --- diff --git a/queue-6.2/drm-add-missing-dp-dsc-extended-capability-definitio.patch b/queue-6.2/drm-add-missing-dp-dsc-extended-capability-definitio.patch new file mode 100644 index 00000000000..129cd814173 --- /dev/null +++ b/queue-6.2/drm-add-missing-dp-dsc-extended-capability-definitio.patch @@ -0,0 +1,72 @@ +From 0fc446a85cc2c8539c890ee37cdd0d2059f1cb7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Nov 2022 11:42:17 +0200 +Subject: drm: Add missing DP DSC extended capability definitions. + +From: Stanislav Lisovskiy + +[ Upstream commit 1482ec00be4a3634aeffbcc799791a723df69339 ] + +Adding DP DSC register definitions, we might need for further +DSC implementation, supporting MST and DP branch pass-through mode. + +v2: - Fixed checkpatch comment warning +v3: - Removed function which is not yet used(Jani Nikula) + +Reviewed-by: Vinod Govindapillai +Acked-by: Maarten Lankhorst +Signed-off-by: Stanislav Lisovskiy +Link: https://patchwork.freedesktop.org/patch/msgid/20221101094222.22091-2-stanislav.lisovskiy@intel.com +Stable-dep-of: 13525645e224 ("drm/dsc: fix drm_edp_dsc_sink_output_bpp() DPCD high byte usage") +Signed-off-by: Sasha Levin +--- + include/drm/display/drm_dp.h | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h +index e934aab357bea..9bc22a02874d9 100644 +--- a/include/drm/display/drm_dp.h ++++ b/include/drm/display/drm_dp.h +@@ -240,6 +240,8 @@ + #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ + # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) + # define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1) ++# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) ++# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) + + #define DP_DSC_REV 0x061 + # define DP_DSC_MAJOR_MASK (0xf << 0) +@@ -278,12 +280,15 @@ + + #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 + # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) ++# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) + + #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ + + #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ + # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) + # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 ++# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 ++# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 + + #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 + # define DP_DSC_RGB (1 << 0) +@@ -345,11 +350,13 @@ + # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) + + #define DP_DSC_BITS_PER_PIXEL_INC 0x06F ++# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f ++# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 + # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 + # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 + # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 + # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 +-# define DP_DSC_BITS_PER_PIXEL_1 0x4 ++# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 + + #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ + # define DP_PSR_IS_SUPPORTED 1 +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-add-minimum-z8-residency-debug-optio.patch b/queue-6.2/drm-amd-display-add-minimum-z8-residency-debug-optio.patch new file mode 100644 index 00000000000..174afd47e70 --- /dev/null +++ b/queue-6.2/drm-amd-display-add-minimum-z8-residency-debug-optio.patch @@ -0,0 +1,70 @@ +From f28ec91077e03bf99b57aa4a713ae84d341b294e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 17 Feb 2023 11:17:50 -0500 +Subject: drm/amd/display: Add minimum Z8 residency debug option + +From: Nicholas Kazlauskas + +[ Upstream commit 0db13eae41fcc67f408dbb3dfda59633c4fa03fb ] + +[Why] +Allows finer control and tuning for debug and profiling. + +[How] +Add the debug option into DC. The default remains the same as before +for now. + +Reviewed-by: Jun Lei +Acked-by: Qingqing Zhuo +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Stable-dep-of: d893f39320e1 ("drm/amd/display: Lowering min Z8 residency time") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dc.h | 1 + + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 + + drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 ++- + 3 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 37998dc0fc144..b519602c054b2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -796,6 +796,7 @@ struct dc_debug_options { + unsigned int force_odm_combine; //bit vector based on otg inst + unsigned int seamless_boot_odm_combine; + unsigned int force_odm_combine_4to1; //bit vector based on otg inst ++ int minimum_z8_residency_time; + bool disable_z9_mpc; + unsigned int force_fclk_khz; + bool enable_tri_buf; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +index 9ffba4c6fe550..5c23c934c9751 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +@@ -887,6 +887,7 @@ static const struct dc_plane_cap plane_cap = { + static const struct dc_debug_options debug_defaults_drv = { + .disable_z10 = false, + .enable_z9_disable_interface = true, ++ .minimum_z8_residency_time = 1000, + .psr_skip_crtc_disable = true, + .disable_dmcu = true, + .force_abm_enable = false, +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index 859dc67a1fb6b..b6b8be74ee0ea 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -973,7 +973,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + struct dc_stream_status *stream_status = &context->stream_status[0]; +- bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0; ++ int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000; ++ bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; + bool is_pwrseq0 = link->link_index == 0; + + if (dc_extended_blank_supported(dc)) { +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-change-default-z8-watermark-values.patch b/queue-6.2/drm-amd-display-change-default-z8-watermark-values.patch new file mode 100644 index 00000000000..f5ae899a8d7 --- /dev/null +++ b/queue-6.2/drm-amd-display-change-default-z8-watermark-values.patch @@ -0,0 +1,43 @@ +From 8970e5642d2b908f020985751abf3c344c2588e1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Apr 2023 17:34:24 -0400 +Subject: drm/amd/display: Change default Z8 watermark values + +From: Leo Chen + +[ Upstream commit 8f586cc16c1fc3c2202c9d54563db8c7ed365f82 ] + +[Why & How] +Previous Z8 watermark values were causing flickering and OTC underflow. +Updating Z8 watermark values based on the measurement. + +Reviewed-by: Nicholas Kazlauskas +Cc: Mario Limonciello +Cc: Alex Deucher +Cc: stable@vger.kernel.org +Acked-by: Alan Liu +Signed-off-by: Leo Chen +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 0c91d8a3de4c3..db06f3b9e637e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -149,8 +149,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { + .num_states = 5, + .sr_exit_time_us = 16.5, + .sr_enter_plus_exit_time_us = 18.5, +- .sr_exit_z8_time_us = 210.0, +- .sr_enter_plus_exit_z8_time_us = 310.0, ++ .sr_exit_z8_time_us = 268.0, ++ .sr_enter_plus_exit_z8_time_us = 393.0, + .writeback_latency_us = 12.0, + .dram_channel_width_bytes = 4, + .round_trip_ping_latency_dcfclk_cycles = 106, +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-fix-z8-support-configurations.patch b/queue-6.2/drm-amd-display-fix-z8-support-configurations.patch new file mode 100644 index 00000000000..b96039ea40b --- /dev/null +++ b/queue-6.2/drm-amd-display-fix-z8-support-configurations.patch @@ -0,0 +1,76 @@ +From ffadcdb7bf8013d96b6d8ccfe9250492af4eb9ea Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Jan 2023 09:49:32 -0500 +Subject: drm/amd/display: Fix Z8 support configurations + +From: Nicholas Kazlauskas + +[ Upstream commit 73dd4ca4b5a01235607231839bd351bbef75a1d2 ] + +[Why] +It's not supported in multi-display, but it is supported in 2nd eDP +screen only. + +[How] +Remove multi display support, restrict number of planes for all +z-states support, but still allow Z8 if we're not using PWRSEQ0. + +Reviewed-by: Charlene Liu +Acked-by: Alex Hung +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Stable-dep-of: d893f39320e1 ("drm/amd/display: Lowering min Z8 residency time") +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index c26da3bb2892b..859dc67a1fb6b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -949,7 +949,6 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + int plane_count; + int i; + unsigned int optimized_min_dst_y_next_start_us; +- bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0; + + plane_count = 0; + optimized_min_dst_y_next_start_us = 0; +@@ -974,6 +973,8 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + struct dc_stream_status *stream_status = &context->stream_status[0]; ++ bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0; ++ bool is_pwrseq0 = link->link_index == 0; + + if (dc_extended_blank_supported(dc)) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { +@@ -986,18 +987,17 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc + } + } + } +- /* zstate only supported on PWRSEQ0 and when there's <2 planes*/ +- if (link->link_index != 0 || stream_status->plane_count > 1) ++ ++ /* Don't support multi-plane configurations */ ++ if (stream_status->plane_count > 1) + return DCN_ZSTATE_SUPPORT_DISALLOW; + +- if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000) ++ if (is_pwrseq0 && (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)) + return DCN_ZSTATE_SUPPORT_ALLOW; +- else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr) ++ else if (is_pwrseq0 && link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr) + return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY; + else + return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW; +- } else if (allow_z8) { +- return DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; + } else { + return DCN_ZSTATE_SUPPORT_DISALLOW; + } +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-lowering-min-z8-residency-time.patch b/queue-6.2/drm-amd-display-lowering-min-z8-residency-time.patch new file mode 100644 index 00000000000..e48f7c3fef6 --- /dev/null +++ b/queue-6.2/drm-amd-display-lowering-min-z8-residency-time.patch @@ -0,0 +1,41 @@ +From 7171239779f9fc34d914fdf2a892a9c1dd89aa0f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 11 Apr 2023 10:49:38 -0400 +Subject: drm/amd/display: Lowering min Z8 residency time + +From: Leo Chen + +[ Upstream commit d893f39320e1248d1c97fde0d6e51e5ea008a76b ] + +[Why & How] +Per HW team request, we're lowering the minimum Z8 +residency time to 2000us. This enables Z8 support for additional +modes we were previously blocking like 2k>60hz + +Cc: stable@vger.kernel.org +Tested-by: Daniel Wheeler +Reviewed-by: Nicholas Kazlauskas +Acked-by: Rodrigo Siqueira +Signed-off-by: Leo Chen +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +index 33d8188d076ab..30129fb9c27a9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +@@ -887,7 +887,7 @@ static const struct dc_plane_cap plane_cap = { + static const struct dc_debug_options debug_defaults_drv = { + .disable_z10 = false, + .enable_z9_disable_interface = true, +- .minimum_z8_residency_time = 3080, ++ .minimum_z8_residency_time = 2000, + .psr_skip_crtc_disable = true, + .disable_dmcu = true, + .force_abm_enable = false, +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-update-minimum-stutter-residency-for.patch b/queue-6.2/drm-amd-display-update-minimum-stutter-residency-for.patch new file mode 100644 index 00000000000..ef3085ab1f5 --- /dev/null +++ b/queue-6.2/drm-amd-display-update-minimum-stutter-residency-for.patch @@ -0,0 +1,43 @@ +From ad96260e2d1d54f0310969b44411e96498e44496 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Feb 2023 10:27:10 -0500 +Subject: drm/amd/display: Update minimum stutter residency for DCN314 Z8 + +From: Nicholas Kazlauskas + +[ Upstream commit 0215ce9057edf69aff9c1a32f4254e1ec297db31 ] + +[Why] +Block periods that are too short as they have the potential to +currently cause hangs in other firmware components on the system. + +[How] +Update the threshold, mostly targeting a block of 4k and downscaling. + +Reviewed-by: Jun Lei +Acked-by: Qingqing Zhuo +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Stable-dep-of: d893f39320e1 ("drm/amd/display: Lowering min Z8 residency time") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +index 5c23c934c9751..33d8188d076ab 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +@@ -887,7 +887,7 @@ static const struct dc_plane_cap plane_cap = { + static const struct dc_debug_options debug_defaults_drv = { + .disable_z10 = false, + .enable_z9_disable_interface = true, +- .minimum_z8_residency_time = 1000, ++ .minimum_z8_residency_time = 3080, + .psr_skip_crtc_disable = true, + .disable_dmcu = true, + .force_abm_enable = false, +-- +2.39.2 + diff --git a/queue-6.2/drm-amd-display-update-z8-sr-exit-enter-latencies.patch b/queue-6.2/drm-amd-display-update-z8-sr-exit-enter-latencies.patch new file mode 100644 index 00000000000..bf02903d4db --- /dev/null +++ b/queue-6.2/drm-amd-display-update-z8-sr-exit-enter-latencies.patch @@ -0,0 +1,44 @@ +From cbec73d93ff6c22e3de4c48b7a6b273357fb0227 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 1 Feb 2023 13:38:05 -0500 +Subject: drm/amd/display: Update Z8 SR exit/enter latencies + +From: Nicholas Kazlauskas + +[ Upstream commit 9b0f51e8449f6f76170fda6a8dd9c417a43ce270 ] + +[Why] +Request from HW team to update the latencies to the new measured values. + +[How] +Update the values in the bounding box. + +Reviewed-by: Charlene Liu +Acked-by: Qingqing Zhuo +Signed-off-by: Nicholas Kazlauskas +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Stable-dep-of: 8f586cc16c1f ("drm/amd/display: Change default Z8 watermark values") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +index 6a1cf6adea77d..0c91d8a3de4c3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +@@ -149,8 +149,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { + .num_states = 5, + .sr_exit_time_us = 16.5, + .sr_enter_plus_exit_time_us = 18.5, +- .sr_exit_z8_time_us = 280.0, +- .sr_enter_plus_exit_z8_time_us = 350.0, ++ .sr_exit_z8_time_us = 210.0, ++ .sr_enter_plus_exit_z8_time_us = 310.0, + .writeback_latency_us = 12.0, + .dram_channel_width_bytes = 4, + .round_trip_ping_latency_dcfclk_cycles = 106, +-- +2.39.2 + diff --git a/queue-6.2/drm-dsc-fix-drm_edp_dsc_sink_output_bpp-dpcd-high-by.patch b/queue-6.2/drm-dsc-fix-drm_edp_dsc_sink_output_bpp-dpcd-high-by.patch new file mode 100644 index 00000000000..7624e375723 --- /dev/null +++ b/queue-6.2/drm-dsc-fix-drm_edp_dsc_sink_output_bpp-dpcd-high-by.patch @@ -0,0 +1,59 @@ +From 1f4719aa49536f45c1f5668f184daed25199cd42 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Apr 2023 16:46:14 +0300 +Subject: drm/dsc: fix drm_edp_dsc_sink_output_bpp() DPCD high byte usage + +From: Jani Nikula + +[ Upstream commit 13525645e2246ebc8a21bd656248d86022a6ee8f ] + +The operator precedence between << and & is wrong, leading to the high +byte being completely ignored. For example, with the 6.4 format, 32 +becomes 0 and 24 becomes 8. Fix it, and remove the slightly confusing +and unnecessary DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT macro while at it. + +Fixes: 0575650077ea ("drm/dp: DRM DP helper/macros to get DP sink DSC parameters") +Cc: Stanislav Lisovskiy +Cc: Manasi Navare +Cc: Anusha Srivatsa +Cc: # v5.0+ +Signed-off-by: Jani Nikula +Reviewed-by: Ankit Nautiyal +Link: https://patchwork.freedesktop.org/patch/msgid/20230406134615.1422509-1-jani.nikula@intel.com +Signed-off-by: Sasha Levin +--- + include/drm/display/drm_dp.h | 1 - + include/drm/display/drm_dp_helper.h | 5 ++--- + 2 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h +index 9bc22a02874d9..50428ba92ce8b 100644 +--- a/include/drm/display/drm_dp.h ++++ b/include/drm/display/drm_dp.h +@@ -286,7 +286,6 @@ + + #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ + # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +-# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 + # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 + # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 + +diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h +index ab55453f2d2cd..ade9df59e156a 100644 +--- a/include/drm/display/drm_dp_helper.h ++++ b/include/drm/display/drm_dp_helper.h +@@ -181,9 +181,8 @@ static inline u16 + drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) + { + return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | +- (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & +- DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << +- DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); ++ ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & ++ DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); + } + + static inline u32 +-- +2.39.2 + diff --git a/queue-6.2/drm-i915-check-pipe-source-size-when-using-skl-scale.patch b/queue-6.2/drm-i915-check-pipe-source-size-when-using-skl-scale.patch new file mode 100644 index 00000000000..a84f4d13443 --- /dev/null +++ b/queue-6.2/drm-i915-check-pipe-source-size-when-using-skl-scale.patch @@ -0,0 +1,71 @@ +From 61b0c7a99f91838b26b05125adde40d7f9e0c535 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 18 Apr 2023 20:55:14 +0300 +Subject: drm/i915: Check pipe source size when using skl+ scalers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +[ Upstream commit d944eafed618a8507270b324ad9d5405bb7f0b3e ] + +The skl+ scalers only sample 12 bits of PIPESRC so we can't +do any plane scaling at all when the pipe source size is >4k. + +Make sure the pipe source size is also below the scaler's src +size limits. Might not be 100% accurate, but should at least be +safe. We can refine the limits later if we discover that recent +hw is less restricted. + +Cc: stable@vger.kernel.org +Tested-by: Ross Zwisler +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-2-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +(cherry picked from commit 691248d4135fe3fae64b4ee0676bc96a7fd6950c) +Signed-off-by: Joonas Lahtinen +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c +index 01e8812936126..fe5c47672580b 100644 +--- a/drivers/gpu/drm/i915/display/skl_scaler.c ++++ b/drivers/gpu/drm/i915/display/skl_scaler.c +@@ -107,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; ++ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); ++ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); + int min_src_w, min_src_h, min_dst_w, min_dst_h; + int max_src_w, max_src_h, max_dst_w, max_dst_h; + +@@ -198,6 +200,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, + return -EINVAL; + } + ++ /* ++ * The pipe scaler does not use all the bits of PIPESRC, at least ++ * on the earlier platforms. So even when we're scaling a plane ++ * the *pipe* source size must not be too large. For simplicity ++ * we assume the limits match the scaler source size limits. Might ++ * not be 100% accurate on all platforms, but good enough for now. ++ */ ++ if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) { ++ drm_dbg_kms(&dev_priv->drm, ++ "scaler_user index %u.%u: pipe src size %ux%u " ++ "is out of scaler range\n", ++ crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); ++ return -EINVAL; ++ } ++ + /* mark this plane as a scaler user in crtc_state */ + scaler_state->scaler_users |= (1 << scaler_user); + drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " +-- +2.39.2 + diff --git a/queue-6.2/drm-i915-disable-sampler-indirect-state-in-bindless-.patch b/queue-6.2/drm-i915-disable-sampler-indirect-state-in-bindless-.patch new file mode 100644 index 00000000000..fff058b6240 --- /dev/null +++ b/queue-6.2/drm-i915-disable-sampler-indirect-state-in-bindless-.patch @@ -0,0 +1,81 @@ +From 07b817d6919c9ff4ce3ad53f53b538ae9a2ed93f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 7 Apr 2023 12:32:37 +0300 +Subject: drm/i915: disable sampler indirect state in bindless heap + +From: Lionel Landwerlin + +[ Upstream commit 81900e3a37750d8c6ad705045310e002f6dd0356 ] + +By default the indirect state sampler data (border colors) are stored +in the same heap as the SAMPLER_STATE structure. For userspace drivers +that can be 2 different heaps (dynamic state heap & bindless sampler +state heap). This means that border colors have to copied in 2 +different places so that the same SAMPLER_STATE structure find the +right data. + +This change is forcing the indirect state sampler data to only be in +the dynamic state pool (more convenient for userspace drivers, they +only have to have one copy of the border colors). This is reproducing +the behavior of the Windows drivers. + +BSpec: 46052 + +Signed-off-by: Lionel Landwerlin +Cc: stable@vger.kernel.org +Reviewed-by: Haridhar Kalvala +Signed-off-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20230407093237.3296286-1-lionel.g.landwerlin@intel.com +(cherry picked from commit 16fc9c08f0ec7b1c95f1ea4a16097acdb3fc943d) +Signed-off-by: Joonas Lahtinen +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + + drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++++++++++++++ + 2 files changed, 20 insertions(+) + +diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +index 0c30738087a79..1d96c36f9efc2 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h ++++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +@@ -1136,6 +1136,7 @@ + #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) + #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) + #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) ++#define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) + + #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) + #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) +diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c +index 09455682967de..620071efb2fc1 100644 +--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c ++++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c +@@ -3035,6 +3035,25 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li + + add_render_compute_tuning_settings(i915, wal); + ++ if (GRAPHICS_VER(i915) >= 11) { ++ /* This is not a Wa (although referred to as ++ * WaSetInidrectStateOverride in places), this allows ++ * applications that reference sampler states through ++ * the BindlessSamplerStateBaseAddress to have their ++ * border color relative to DynamicStateBaseAddress ++ * rather than BindlessSamplerStateBaseAddress. ++ * ++ * Otherwise SAMPLER_STATE border colors have to be ++ * copied in multiple heaps (DynamicStateBaseAddress & ++ * BindlessSamplerStateBaseAddress) ++ * ++ * BSpec: 46052 ++ */ ++ wa_mcr_masked_en(wal, ++ GEN10_SAMPLER_MODE, ++ GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); ++ } ++ + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) + /* Wa_14017856879 */ +-- +2.39.2 + diff --git a/queue-6.2/drm-i915-mtl-add-wa_14017856879.patch b/queue-6.2/drm-i915-mtl-add-wa_14017856879.patch new file mode 100644 index 00000000000..e8efa746af4 --- /dev/null +++ b/queue-6.2/drm-i915-mtl-add-wa_14017856879.patch @@ -0,0 +1,57 @@ +From 7fae1843606648d019d02bc2e7c5e542d6eff343 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Apr 2023 23:02:20 +0530 +Subject: drm/i915/mtl: Add Wa_14017856879 + +From: Haridhar Kalvala + +[ Upstream commit 4b51210f98c2b89ce37aede5b8dc5105be0572c6 ] + +Wa_14017856879 implementation for mtl. + +Bspec: 46046 + +Signed-off-by: Haridhar Kalvala +Reviewed-by: Gustavo Sousa +Signed-off-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20230404173220.3175577-1-haridhar.kalvala@intel.com +Stable-dep-of: 81900e3a3775 ("drm/i915: disable sampler indirect state in bindless heap") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ + drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +index cd45a45066ccb..0c30738087a79 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h ++++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +@@ -1162,7 +1162,9 @@ + #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) + + #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) ++#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) + #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) ++#define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) + + #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) + #define FLOW_CONTROL_ENABLE REG_BIT(15) +diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c +index 526fb9cc36b9b..09455682967de 100644 +--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c ++++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c +@@ -3035,6 +3035,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li + + add_render_compute_tuning_settings(i915, wal); + ++ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || ++ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) ++ /* Wa_14017856879 */ ++ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); ++ + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) + /* +-- +2.39.2 + diff --git a/queue-6.2/drm-i915-mtl-add-workarounds-wa_14017066071-and-wa_1.patch b/queue-6.2/drm-i915-mtl-add-workarounds-wa_14017066071-and-wa_1.patch new file mode 100644 index 00000000000..3445f381352 --- /dev/null +++ b/queue-6.2/drm-i915-mtl-add-workarounds-wa_14017066071-and-wa_1.patch @@ -0,0 +1,62 @@ +From 0b013c0a3a79ab144c0ff9dbd92dab8d48a84c8b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Mar 2023 18:23:35 -0300 +Subject: drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 + +From: Radhakrishna Sripada + +[ Upstream commit 5fba65efa7cfb8cef227a2c555deb10327a5e27b ] + +Both workarounds require the same implementation and apply to MTL P and +M from stepping A0 to B0 (exclusive). + +v2: + - Remove unrelated brace removal. (Matt) + +Signed-off-by: Radhakrishna Sripada +Signed-off-by: Gustavo Sousa +Reviewed-by: Matt Roper +Signed-off-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@intel.com +Stable-dep-of: 81900e3a3775 ("drm/i915: disable sampler indirect state in bindless heap") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + + drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++ + 2 files changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +index 9758b0b635601..cd45a45066ccb 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h ++++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h +@@ -1135,6 +1135,7 @@ + #define ENABLE_SMALLPL REG_BIT(15) + #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) + #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) ++#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) + + #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) + #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) +diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c +index e13052c5dae19..526fb9cc36b9b 100644 +--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c ++++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c +@@ -3035,6 +3035,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li + + add_render_compute_tuning_settings(i915, wal); + ++ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || ++ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) ++ /* ++ * Wa_14017066071 ++ * Wa_14017654203 ++ */ ++ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, ++ MTL_DISABLE_SAMPLER_SC_OOO); ++ + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || + IS_PONTEVECCHIO(i915) || +-- +2.39.2 + diff --git a/queue-6.2/drm-i915-mtl-update-scaler-source-and-destination-li.patch b/queue-6.2/drm-i915-mtl-update-scaler-source-and-destination-li.patch new file mode 100644 index 00000000000..4cf44d57c39 --- /dev/null +++ b/queue-6.2/drm-i915-mtl-update-scaler-source-and-destination-li.patch @@ -0,0 +1,96 @@ +From b4d08cc1fdcfc616d72f96e57fc4d801be086396 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Dec 2022 15:05:09 +0200 +Subject: drm/i915/mtl: update scaler source and destination limits for MTL +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Animesh Manna + +[ Upstream commit f840834a8b60ffd305f03a53007605ba4dfbbc4b ] + +The max source and destination limits for scalers in MTL have changed. +Use the new values accordingly. + +Signed-off-by: José Roberto de Souza +Signed-off-by: Animesh Manna +Signed-off-by: Luca Coelho +Reviewed-by: Stanislav Lisovskiy +Signed-off-by: Radhakrishna Sripada +Link: https://patchwork.freedesktop.org/patch/msgid/20221223130509.43245-3-luciano.coelho@intel.com +Stable-dep-of: d944eafed618 ("drm/i915: Check pipe source size when using skl+ scalers") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++----- + 1 file changed, 32 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c +index d7390067b7d4c..01e8812936126 100644 +--- a/drivers/gpu/drm/i915/display/skl_scaler.c ++++ b/drivers/gpu/drm/i915/display/skl_scaler.c +@@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) + #define ICL_MAX_SRC_H 4096 + #define ICL_MAX_DST_W 5120 + #define ICL_MAX_DST_H 4096 ++#define MTL_MAX_SRC_W 4096 ++#define MTL_MAX_SRC_H 8192 ++#define MTL_MAX_DST_W 8192 ++#define MTL_MAX_DST_H 8192 + #define SKL_MIN_YUV_420_SRC_W 16 + #define SKL_MIN_YUV_420_SRC_H 16 + +@@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; ++ int min_src_w, min_src_h, min_dst_w, min_dst_h; ++ int max_src_w, max_src_h, max_dst_w, max_dst_h; + + /* + * Src coordinates are already rotated by 270 degrees for +@@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, + return -EINVAL; + } + ++ min_src_w = SKL_MIN_SRC_W; ++ min_src_h = SKL_MIN_SRC_H; ++ min_dst_w = SKL_MIN_DST_W; ++ min_dst_h = SKL_MIN_DST_H; ++ ++ if (DISPLAY_VER(dev_priv) < 11) { ++ max_src_w = SKL_MAX_SRC_W; ++ max_src_h = SKL_MAX_SRC_H; ++ max_dst_w = SKL_MAX_DST_W; ++ max_dst_h = SKL_MAX_DST_H; ++ } else if (DISPLAY_VER(dev_priv) < 14) { ++ max_src_w = ICL_MAX_SRC_W; ++ max_src_h = ICL_MAX_SRC_H; ++ max_dst_w = ICL_MAX_DST_W; ++ max_dst_h = ICL_MAX_DST_H; ++ } else { ++ max_src_w = MTL_MAX_SRC_W; ++ max_src_h = MTL_MAX_SRC_H; ++ max_dst_w = MTL_MAX_DST_W; ++ max_dst_h = MTL_MAX_DST_H; ++ } ++ + /* range checks */ +- if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || +- dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || +- (DISPLAY_VER(dev_priv) >= 11 && +- (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || +- dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || +- (DISPLAY_VER(dev_priv) < 11 && +- (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || +- dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { ++ if (src_w < min_src_w || src_h < min_src_h || ++ dst_w < min_dst_w || dst_h < min_dst_h || ++ src_w > max_src_w || src_h > max_src_h || ++ dst_w > max_dst_w || dst_h > max_dst_h) { + drm_dbg_kms(&dev_priv->drm, + "scaler_user index %u.%u: src %ux%u dst %ux%u " + "size is out of scaler range\n", +-- +2.39.2 + diff --git a/queue-6.2/series b/queue-6.2/series index 0eab3e4360b..50782b33cc2 100644 --- a/queue-6.2/series +++ b/queue-6.2/series @@ -208,3 +208,16 @@ hid-wacom-insert-timestamp-to-packed-bluetooth-bt-events.patch fs-ntfs3-fix-null-ptr-deref-on-inode-i_op-in-ntfs_lookup.patch fs-ntfs3-refactoring-of-various-minor-issues.patch drm-msm-adreno-adreno_gpu-use-suspend-instead-of-idle-on-load-error.patch +drm-i915-mtl-add-workarounds-wa_14017066071-and-wa_1.patch +drm-i915-mtl-add-wa_14017856879.patch +drm-i915-disable-sampler-indirect-state-in-bindless-.patch +drm-i915-mtl-update-scaler-source-and-destination-li.patch +drm-i915-check-pipe-source-size-when-using-skl-scale.patch +drm-amd-display-fix-z8-support-configurations.patch +drm-amd-display-add-minimum-z8-residency-debug-optio.patch +drm-amd-display-update-minimum-stutter-residency-for.patch +drm-amd-display-lowering-min-z8-residency-time.patch +drm-amd-display-update-z8-sr-exit-enter-latencies.patch +drm-amd-display-change-default-z8-watermark-values.patch +drm-add-missing-dp-dsc-extended-capability-definitio.patch +drm-dsc-fix-drm_edp_dsc_sink_output_bpp-dpcd-high-by.patch