From: Konrad Dybcio Date: Mon, 3 Jul 2023 18:20:05 +0000 (+0200) Subject: dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs X-Git-Tag: v6.6-rc1~130^2~6^2~24^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=238e192bedd9b57f8ed026788956387350f2ccb9;p=thirdparty%2Flinux.git dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by: Krzysztof Kozlowski Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58fd..b5456a64d4213 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1