From: Chris Packham Date: Fri, 12 Jul 2019 04:46:58 +0000 (+0100) Subject: ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs X-Git-Tag: v5.4-rc1~79^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=23d103ae3e061b466dc68dd10a035dcd3b2de99a;p=thirdparty%2Fkernel%2Flinux.git ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs The Armada 38x and other integrated SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the Armada XP SoCs. This means that the definition of "full" and "half" width is reduced from 64/32 to 32/16. Signed-off-by: Chris Packham Signed-off-by: Russell King --- diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c index 3759a4fbbdee5..7f227bdcbc845 100644 --- a/drivers/edac/armada_xp_edac.c +++ b/drivers/edac/armada_xp_edac.c @@ -332,6 +332,11 @@ static int axp_mc_probe(struct platform_device *pdev) axp_mc_read_config(mci); + /* These SoCs have a reduced width bus */ + if (of_machine_is_compatible("marvell,armada380") || + of_machine_is_compatible("marvell,armadaxp-98dx3236")) + drvdata->width /= 2; + /* configure SBE threshold */ /* it seems that SBEs are not captured otherwise */ writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);