From: Joel Stanley Date: Wed, 4 Jun 2025 02:54:48 +0000 (+0930) Subject: hw/riscv/virt: Use setprop_sized_cells for pcie X-Git-Tag: v10.1.0-rc0~31^2~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2454fc95ece3c73f649e21621775bcbe859d28ec;p=thirdparty%2Fqemu.git hw/riscv/virt: Use setprop_sized_cells for pcie The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20250604025450.85327-13-joel@jms.id.au> Signed-off-by: Alistair Francis --- diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67490c5c693..47e573f85ab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -894,8 +894,8 @@ static void create_fdt_pcie(RISCVVirtState *s, if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, - s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, + s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,