From: Greg Kroah-Hartman Date: Mon, 23 Sep 2013 22:47:32 +0000 (-0700) Subject: 3.11-stable patches X-Git-Tag: v3.0.97~21 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=24654f2c93ad74e4e25083d47c9a4afd8f287164;p=thirdparty%2Fkernel%2Fstable-queue.git 3.11-stable patches added patches: asoc-mc13783-add-spi-errata-fix.patch asoc-wm8960-fix-pll-register-writes.patch introduce-save_altstack_ex-to-unbreak-x86-smap.patch sched-x86-optimize-switch_mm-for-multi-threaded-workloads.patch x86-amd_nb-clarify-f15h-model-30h-gart-and-l3-support.patch x86-mce-pay-no-attention-to-f-bit-in-mcacod-when-parsing-uc-errors.patch x86-smap-handle-csum_partial_copy_-_user.patch --- diff --git a/queue-3.11/asoc-mc13783-add-spi-errata-fix.patch b/queue-3.11/asoc-mc13783-add-spi-errata-fix.patch new file mode 100644 index 00000000000..8cd26d0c148 --- /dev/null +++ b/queue-3.11/asoc-mc13783-add-spi-errata-fix.patch @@ -0,0 +1,41 @@ +From 9f6f0afbb9fdabf6dcac642dfec457f28981e3f8 Mon Sep 17 00:00:00 2001 +From: Steffen Trumtrar +Date: Mon, 9 Sep 2013 18:09:12 +0200 +Subject: ASoC: mc13783: add spi errata fix + +From: Steffen Trumtrar + +commit 9f6f0afbb9fdabf6dcac642dfec457f28981e3f8 upstream. + +The MC13783 Chip Errata, Rev. 4 says, that depending on SPI clock +and main audio clock speed, the Audio Codec or Stereo DAC do sometimes +not start when programmed to do so. This is due to an internal clock +timing issue related to the loading of the SPI bits into the audio block. + +On an i.MX27 based system, this issue lead to switched audio channels under +certain circumstances: RTC + Touch + Audio are used and loaded at startup. + +The mentioned workaround of writing registers 40 and 41 two times is implemented +here. + +Signed-off-by: Steffen Trumtrar +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/mc13783.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/sound/soc/codecs/mc13783.c ++++ b/sound/soc/codecs/mc13783.c +@@ -126,6 +126,10 @@ static int mc13783_write(struct snd_soc_ + + ret = mc13xxx_reg_write(priv->mc13xxx, reg, value); + ++ /* include errata fix for spi audio problems */ ++ if (reg == MC13783_AUDIO_CODEC || reg == MC13783_AUDIO_DAC) ++ ret = mc13xxx_reg_write(priv->mc13xxx, reg, value); ++ + mc13xxx_unlock(priv->mc13xxx); + + return ret; diff --git a/queue-3.11/asoc-wm8960-fix-pll-register-writes.patch b/queue-3.11/asoc-wm8960-fix-pll-register-writes.patch new file mode 100644 index 00000000000..85dbdf2c8cb --- /dev/null +++ b/queue-3.11/asoc-wm8960-fix-pll-register-writes.patch @@ -0,0 +1,35 @@ +From 85fa532b6ef920b32598df86b194571a7059a77c Mon Sep 17 00:00:00 2001 +From: Mike Dyer +Date: Fri, 16 Aug 2013 18:36:28 +0100 +Subject: ASoC: wm8960: Fix PLL register writes + +From: Mike Dyer + +commit 85fa532b6ef920b32598df86b194571a7059a77c upstream. + +Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part +should be split across each register in 8bit chunks. + +Signed-off-by: Mike Dyer +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/wm8960.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/sound/soc/codecs/wm8960.c ++++ b/sound/soc/codecs/wm8960.c +@@ -857,9 +857,9 @@ static int wm8960_set_dai_pll(struct snd + if (pll_div.k) { + reg |= 0x20; + +- snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f); +- snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff); +- snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff); ++ snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); ++ snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); ++ snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); + } + snd_soc_write(codec, WM8960_PLL1, reg); + diff --git a/queue-3.11/introduce-save_altstack_ex-to-unbreak-x86-smap.patch b/queue-3.11/introduce-save_altstack_ex-to-unbreak-x86-smap.patch new file mode 100644 index 00000000000..67679cfa1ee --- /dev/null +++ b/queue-3.11/introduce-save_altstack_ex-to-unbreak-x86-smap.patch @@ -0,0 +1,107 @@ +From bd1c149aa9915b9abb6d83d0f01dfd2ace0680b5 Mon Sep 17 00:00:00 2001 +From: Al Viro +Date: Sun, 1 Sep 2013 20:35:01 +0100 +Subject: Introduce [compat_]save_altstack_ex() to unbreak x86 SMAP + +From: Al Viro + +commit bd1c149aa9915b9abb6d83d0f01dfd2ace0680b5 upstream. + +For performance reasons, when SMAP is in use, SMAP is left open for an +entire put_user_try { ... } put_user_catch(); block, however, calling +__put_user() in the middle of that block will close SMAP as the +STAC..CLAC constructs intentionally do not nest. + +Furthermore, using __put_user() rather than put_user_ex() here is bad +for performance. + +Thus, introduce new [compat_]save_altstack_ex() helpers that replace +__[compat_]save_altstack() for x86, being currently the only +architecture which supports put_user_try { ... } put_user_catch(). + +Reported-by: H. Peter Anvin +Signed-off-by: Al Viro +Signed-off-by: H. Peter Anvin +Link: http://lkml.kernel.org/n/tip-es5p6y64if71k8p5u08agv9n@git.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/ia32/ia32_signal.c | 2 +- + arch/x86/kernel/signal.c | 6 +++--- + include/linux/compat.h | 7 +++++++ + include/linux/signal.h | 8 ++++++++ + 4 files changed, 19 insertions(+), 4 deletions(-) + +--- a/arch/x86/ia32/ia32_signal.c ++++ b/arch/x86/ia32/ia32_signal.c +@@ -457,7 +457,7 @@ int ia32_setup_rt_frame(int sig, struct + else + put_user_ex(0, &frame->uc.uc_flags); + put_user_ex(0, &frame->uc.uc_link); +- err |= __compat_save_altstack(&frame->uc.uc_stack, regs->sp); ++ compat_save_altstack_ex(&frame->uc.uc_stack, regs->sp); + + if (ksig->ka.sa.sa_flags & SA_RESTORER) + restorer = ksig->ka.sa.sa_restorer; +--- a/arch/x86/kernel/signal.c ++++ b/arch/x86/kernel/signal.c +@@ -358,7 +358,7 @@ static int __setup_rt_frame(int sig, str + else + put_user_ex(0, &frame->uc.uc_flags); + put_user_ex(0, &frame->uc.uc_link); +- err |= __save_altstack(&frame->uc.uc_stack, regs->sp); ++ save_altstack_ex(&frame->uc.uc_stack, regs->sp); + + /* Set up to return from userspace. */ + restorer = VDSO32_SYMBOL(current->mm->context.vdso, rt_sigreturn); +@@ -423,7 +423,7 @@ static int __setup_rt_frame(int sig, str + else + put_user_ex(0, &frame->uc.uc_flags); + put_user_ex(0, &frame->uc.uc_link); +- err |= __save_altstack(&frame->uc.uc_stack, regs->sp); ++ save_altstack_ex(&frame->uc.uc_stack, regs->sp); + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ +@@ -490,7 +490,7 @@ static int x32_setup_rt_frame(struct ksi + else + put_user_ex(0, &frame->uc.uc_flags); + put_user_ex(0, &frame->uc.uc_link); +- err |= __compat_save_altstack(&frame->uc.uc_stack, regs->sp); ++ compat_save_altstack_ex(&frame->uc.uc_stack, regs->sp); + put_user_ex(0, &frame->uc.uc__pad0); + + if (ksig->ka.sa.sa_flags & SA_RESTORER) { +--- a/include/linux/compat.h ++++ b/include/linux/compat.h +@@ -669,6 +669,13 @@ asmlinkage long compat_sys_sigaltstack(c + + int compat_restore_altstack(const compat_stack_t __user *uss); + int __compat_save_altstack(compat_stack_t __user *, unsigned long); ++#define compat_save_altstack_ex(uss, sp) do { \ ++ compat_stack_t __user *__uss = uss; \ ++ struct task_struct *t = current; \ ++ put_user_ex(ptr_to_compat((void __user *)t->sas_ss_sp), &__uss->ss_sp); \ ++ put_user_ex(sas_ss_flags(sp), &__uss->ss_flags); \ ++ put_user_ex(t->sas_ss_size, &__uss->ss_size); \ ++} while (0); + + asmlinkage long compat_sys_sched_rr_get_interval(compat_pid_t pid, + struct compat_timespec __user *interval); +--- a/include/linux/signal.h ++++ b/include/linux/signal.h +@@ -434,6 +434,14 @@ void signals_init(void); + int restore_altstack(const stack_t __user *); + int __save_altstack(stack_t __user *, unsigned long); + ++#define save_altstack_ex(uss, sp) do { \ ++ stack_t __user *__uss = uss; \ ++ struct task_struct *t = current; \ ++ put_user_ex((void __user *)t->sas_ss_sp, &__uss->ss_sp); \ ++ put_user_ex(sas_ss_flags(sp), &__uss->ss_flags); \ ++ put_user_ex(t->sas_ss_size, &__uss->ss_size); \ ++} while (0); ++ + #ifdef CONFIG_PROC_FS + struct seq_file; + extern void render_sigset_t(struct seq_file *, const char *, sigset_t *); diff --git a/queue-3.11/sched-x86-optimize-switch_mm-for-multi-threaded-workloads.patch b/queue-3.11/sched-x86-optimize-switch_mm-for-multi-threaded-workloads.patch new file mode 100644 index 00000000000..2c3d55db02c --- /dev/null +++ b/queue-3.11/sched-x86-optimize-switch_mm-for-multi-threaded-workloads.patch @@ -0,0 +1,90 @@ +From 8f898fbbe5ee5e20a77c4074472a1fd088dc47d1 Mon Sep 17 00:00:00 2001 +From: Rik van Riel +Date: Wed, 31 Jul 2013 22:14:21 -0400 +Subject: sched/x86: Optimize switch_mm() for multi-threaded workloads + +From: Rik van Riel + +commit 8f898fbbe5ee5e20a77c4074472a1fd088dc47d1 upstream. + +Dick Fowles, Don Zickus and Joe Mario have been working on +improvements to perf, and noticed heavy cache line contention +on the mm_cpumask, running linpack on a 60 core / 120 thread +system. + +The cause turned out to be unnecessary atomic accesses to the +mm_cpumask. When in lazy TLB mode, the CPU is only removed from +the mm_cpumask if there is a TLB flush event. + +Most of the time, no such TLB flush happens, and the kernel +skips the TLB reload. It can also skip the atomic memory +set & test. + +Here is a summary of Joe's test results: + + * The __schedule function dropped from 24% of all program cycles down + to 5.5%. + + * The cacheline contention/hotness for accesses to that bitmask went + from being the 1st/2nd hottest - down to the 84th hottest (0.3% of + all shared misses which is now quite cold) + + * The average load latency for the bit-test-n-set instruction in + __schedule dropped from 10k-15k cycles down to an average of 600 cycles. + + * The linpack program results improved from 133 GFlops to 144 GFlops. + Peak GFlops rose from 133 to 153. + +Reported-by: Don Zickus +Reported-by: Joe Mario +Tested-by: Joe Mario +Signed-off-by: Rik van Riel +Reviewed-by: Paul Turner +Acked-by: Linus Torvalds +Link: http://lkml.kernel.org/r/20130731221421.616d3d20@annuminas.surriel.com +[ Made the comments consistent around the modified code. ] +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/include/asm/mmu_context.h | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +--- a/arch/x86/include/asm/mmu_context.h ++++ b/arch/x86/include/asm/mmu_context.h +@@ -45,22 +45,28 @@ static inline void switch_mm(struct mm_s + /* Re-load page tables */ + load_cr3(next->pgd); + +- /* stop flush ipis for the previous mm */ ++ /* Stop flush ipis for the previous mm */ + cpumask_clear_cpu(cpu, mm_cpumask(prev)); + +- /* +- * load the LDT, if the LDT is different: +- */ ++ /* Load the LDT, if the LDT is different: */ + if (unlikely(prev->context.ldt != next->context.ldt)) + load_LDT_nolock(&next->context); + } + #ifdef CONFIG_SMP +- else { ++ else { + this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK); + BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next); + +- if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) { +- /* We were in lazy tlb mode and leave_mm disabled ++ if (!cpumask_test_cpu(cpu, mm_cpumask(next))) { ++ /* ++ * On established mms, the mm_cpumask is only changed ++ * from irq context, from ptep_clear_flush() while in ++ * lazy tlb mode, and here. Irqs are blocked during ++ * schedule, protecting us from simultaneous changes. ++ */ ++ cpumask_set_cpu(cpu, mm_cpumask(next)); ++ /* ++ * We were in lazy tlb mode and leave_mm disabled + * tlb flush IPI delivery. We must reload CR3 + * to make sure to use no freed page tables. + */ diff --git a/queue-3.11/series b/queue-3.11/series index 0ee6e0212eb..f1c672274e4 100644 --- a/queue-3.11/series +++ b/queue-3.11/series @@ -46,3 +46,10 @@ usb-config-desc.blength-may-not-exceed-amount-of-data-returned-by-the-device.pat usb-handle-lpm-errors-during-device-suspend-correctly.patch usb-don-t-check-pm-qos-no_power_off-flag-in-usb_port_suspend.patch rculist-list_first_or_null_rcu-should-use-list_entry_rcu.patch +asoc-wm8960-fix-pll-register-writes.patch +asoc-mc13783-add-spi-errata-fix.patch +x86-smap-handle-csum_partial_copy_-_user.patch +introduce-save_altstack_ex-to-unbreak-x86-smap.patch +x86-amd_nb-clarify-f15h-model-30h-gart-and-l3-support.patch +x86-mce-pay-no-attention-to-f-bit-in-mcacod-when-parsing-uc-errors.patch +sched-x86-optimize-switch_mm-for-multi-threaded-workloads.patch diff --git a/queue-3.11/x86-amd_nb-clarify-f15h-model-30h-gart-and-l3-support.patch b/queue-3.11/x86-amd_nb-clarify-f15h-model-30h-gart-and-l3-support.patch new file mode 100644 index 00000000000..d65eeb835af --- /dev/null +++ b/queue-3.11/x86-amd_nb-clarify-f15h-model-30h-gart-and-l3-support.patch @@ -0,0 +1,63 @@ +From 7d64ac6422092adbbdaa279ab32f9d4c90a84558 Mon Sep 17 00:00:00 2001 +From: Aravind Gopalakrishnan +Date: Fri, 2 Aug 2013 17:43:03 -0500 +Subject: x86, amd_nb: Clarify F15h, model 30h GART and L3 support + +From: Aravind Gopalakrishnan + +commit 7d64ac6422092adbbdaa279ab32f9d4c90a84558 upstream. + +F15h, models 0x30 and later don't have a GART. Note that. Also check +CPUID leaf 0x80000006 for L3 prescence because there are models which +don't sport an L3 cache. + +Signed-off-by: Aravind Gopalakrishnan +[ Boris: rewrite commit message, cleanup comments. ] +Signed-off-by: Borislav Petkov +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/amd_nb.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/amd_nb.c ++++ b/arch/x86/kernel/amd_nb.c +@@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_i + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, + {} + }; +@@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); + + static const struct pci_device_id amd_nb_link_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, + {} + }; +@@ -81,13 +83,20 @@ int amd_cache_northbridges(void) + next_northbridge(misc, amd_nb_misc_ids); + node_to_amd_nb(i)->link = link = + next_northbridge(link, amd_nb_link_ids); +- } ++ } + ++ /* GART present only on Fam15h upto model 0fh */ + if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || +- boot_cpu_data.x86 == 0x15) ++ (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) + amd_northbridges.flags |= AMD_NB_GART; + + /* ++ * Check for L3 cache presence. ++ */ ++ if (!cpuid_edx(0x80000006)) ++ return 0; ++ ++ /* + * Some CPU families support L3 Cache Index Disable. There are some + * limitations because of E382 and E388 on family 0x10. + */ diff --git a/queue-3.11/x86-mce-pay-no-attention-to-f-bit-in-mcacod-when-parsing-uc-errors.patch b/queue-3.11/x86-mce-pay-no-attention-to-f-bit-in-mcacod-when-parsing-uc-errors.patch new file mode 100644 index 00000000000..d14ddcd4bdd --- /dev/null +++ b/queue-3.11/x86-mce-pay-no-attention-to-f-bit-in-mcacod-when-parsing-uc-errors.patch @@ -0,0 +1,50 @@ +From 0ca06c0857aee11911f91621db14498496f2c2cd Mon Sep 17 00:00:00 2001 +From: Tony Luck +Date: Wed, 24 Jul 2013 13:54:20 -0700 +Subject: x86/mce: Pay no attention to 'F' bit in MCACOD when parsing 'UC' errors + +From: Tony Luck + +commit 0ca06c0857aee11911f91621db14498496f2c2cd upstream. + +The 0x1000 bit of the MCACOD field of machine check MCi_STATUS +registers is only defined for corrected errors (where it means +that hardware may be filtering errors see SDM section 15.9.2.1). + +For uncorrected errors it may, or may not be set - so we should mask +it out when checking for the architecturaly defined recoverable +error signatures (see SDM 15.9.3.1 and 15.9.3.2) + +Acked-by: Naveen N. Rao +Signed-off-by: Tony Luck +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/include/asm/mce.h | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/mce.h ++++ b/arch/x86/include/asm/mce.h +@@ -32,11 +32,20 @@ + #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ + #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ + #define MCI_STATUS_AR (1ULL<<55) /* Action required */ +-#define MCACOD 0xffff /* MCA Error Code */ ++ ++/* ++ * Note that the full MCACOD field of IA32_MCi_STATUS MSR is ++ * bits 15:0. But bit 12 is the 'F' bit, defined for corrected ++ * errors to indicate that errors are being filtered by hardware. ++ * We should mask out bit 12 when looking for specific signatures ++ * of uncorrected errors - so the F bit is deliberately skipped ++ * in this #define. ++ */ ++#define MCACOD 0xefff /* MCA Error Code */ + + /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ + #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ +-#define MCACOD_SCRUBMSK 0xfff0 ++#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ + #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ + #define MCACOD_DATA 0x0134 /* Data Load */ + #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ diff --git a/queue-3.11/x86-smap-handle-csum_partial_copy_-_user.patch b/queue-3.11/x86-smap-handle-csum_partial_copy_-_user.patch new file mode 100644 index 00000000000..742b3e7c855 --- /dev/null +++ b/queue-3.11/x86-smap-handle-csum_partial_copy_-_user.patch @@ -0,0 +1,109 @@ +From 7263dda41b5a28ae6566fd126d9b06ada73dd721 Mon Sep 17 00:00:00 2001 +From: "H. Peter Anvin" +Date: Fri, 30 Aug 2013 15:43:03 -0700 +Subject: x86, smap: Handle csum_partial_copy_*_user() + +From: "H. Peter Anvin" + +commit 7263dda41b5a28ae6566fd126d9b06ada73dd721 upstream. + +Add SMAP annotations to csum_partial_copy_to/from_user(). These +functions legitimately access user space and thus need to set the AC +flag. + +TODO: add explicit checks that the side with the kernel space pointer +really points into kernel space. + +Signed-off-by: H. Peter Anvin +Link: http://lkml.kernel.org/n/tip-2aps0u00eer658fd5xyanan7@git.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/include/asm/checksum_32.h | 22 +++++++++++++++++----- + arch/x86/lib/csum-wrappers_64.c | 12 ++++++++++-- + 2 files changed, 27 insertions(+), 7 deletions(-) + +--- a/arch/x86/include/asm/checksum_32.h ++++ b/arch/x86/include/asm/checksum_32.h +@@ -49,9 +49,15 @@ static inline __wsum csum_partial_copy_f + int len, __wsum sum, + int *err_ptr) + { ++ __wsum ret; ++ + might_sleep(); +- return csum_partial_copy_generic((__force void *)src, dst, +- len, sum, err_ptr, NULL); ++ stac(); ++ ret = csum_partial_copy_generic((__force void *)src, dst, ++ len, sum, err_ptr, NULL); ++ clac(); ++ ++ return ret; + } + + /* +@@ -176,10 +182,16 @@ static inline __wsum csum_and_copy_to_us + int len, __wsum sum, + int *err_ptr) + { ++ __wsum ret; ++ + might_sleep(); +- if (access_ok(VERIFY_WRITE, dst, len)) +- return csum_partial_copy_generic(src, (__force void *)dst, +- len, sum, NULL, err_ptr); ++ if (access_ok(VERIFY_WRITE, dst, len)) { ++ stac(); ++ ret = csum_partial_copy_generic(src, (__force void *)dst, ++ len, sum, NULL, err_ptr); ++ clac(); ++ return ret; ++ } + + if (len) + *err_ptr = -EFAULT; +--- a/arch/x86/lib/csum-wrappers_64.c ++++ b/arch/x86/lib/csum-wrappers_64.c +@@ -6,6 +6,7 @@ + */ + #include + #include ++#include + + /** + * csum_partial_copy_from_user - Copy and checksum from user space. +@@ -52,8 +53,10 @@ csum_partial_copy_from_user(const void _ + len -= 2; + } + } ++ stac(); + isum = csum_partial_copy_generic((__force const void *)src, + dst, len, isum, errp, NULL); ++ clac(); + if (unlikely(*errp)) + goto out_err; + +@@ -82,6 +85,8 @@ __wsum + csum_partial_copy_to_user(const void *src, void __user *dst, + int len, __wsum isum, int *errp) + { ++ __wsum ret; ++ + might_sleep(); + + if (unlikely(!access_ok(VERIFY_WRITE, dst, len))) { +@@ -105,8 +110,11 @@ csum_partial_copy_to_user(const void *sr + } + + *errp = 0; +- return csum_partial_copy_generic(src, (void __force *)dst, +- len, isum, NULL, errp); ++ stac(); ++ ret = csum_partial_copy_generic(src, (void __force *)dst, ++ len, isum, NULL, errp); ++ clac(); ++ return ret; + } + EXPORT_SYMBOL(csum_partial_copy_to_user); +