From: Greg Kroah-Hartman Date: Fri, 28 Oct 2016 14:32:02 +0000 (-0400) Subject: 4.4-stable patches X-Git-Tag: v4.4.29~24 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=24f1f786c99d65248ec80daa2e9714c257788844;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch --- diff --git a/queue-4.4/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch b/queue-4.4/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch new file mode 100644 index 00000000000..f8dc7dead38 --- /dev/null +++ b/queue-4.4/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch @@ -0,0 +1,91 @@ +From 4e4d3814a9bb4d71cd3ff0701d8d7041edefd8f0 Mon Sep 17 00:00:00 2001 +From: Paulo Zanoni +Date: Thu, 22 Sep 2016 18:00:30 -0300 +Subject: drm/i915/gen9: fix the WaWmMemoryReadLatency implementation + +From: Paulo Zanoni + +commit 4e4d3814a9bb4d71cd3ff0701d8d7041edefd8f0 upstream. + +Bspec says: + "The mailbox response data may not account for memory read latency. + If the mailbox response data for level 0 is 0us, add 2 microseconds + to the result for each valid level." + +This means we should only do the +2 in case wm[0] == 0, not always. + +So split the sanitizing implementation from the WA implementation and +fix the WA implementation. + +v2: Add Fixes tag (Maarten). + +Fixes: 367294be7c25 ("drm/i915/gen9: Add 2us read latency to WM level") +Cc: Vandana Kannan +Reviewed-by: Maarten Lankhorst +Signed-off-by: Paulo Zanoni +Link: http://patchwork.freedesktop.org/patch/msgid/1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com +(cherry picked from commit 0727e40a48a1d08cf54ce2c01e120864b92e59bf) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_pm.c | 42 ++++++++++++++++++++-------------------- + 1 file changed, 22 insertions(+), 20 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -2097,32 +2097,34 @@ static void intel_read_wm_latency(struct + GEN9_MEM_LATENCY_LEVEL_MASK; + + /* ++ * If a level n (n > 1) has a 0us latency, all levels m (m >= n) ++ * need to be disabled. We make sure to sanitize the values out ++ * of the punit to satisfy this requirement. ++ */ ++ for (level = 1; level <= max_level; level++) { ++ if (wm[level] == 0) { ++ for (i = level + 1; i <= max_level; i++) ++ wm[i] = 0; ++ break; ++ } ++ } ++ ++ /* + * WaWmMemoryReadLatency:skl + * + * punit doesn't take into account the read latency so we need +- * to add 2us to the various latency levels we retrieve from +- * the punit. +- * - W0 is a bit special in that it's the only level that +- * can't be disabled if we want to have display working, so +- * we always add 2us there. +- * - For levels >=1, punit returns 0us latency when they are +- * disabled, so we respect that and don't add 2us then +- * +- * Additionally, if a level n (n > 1) has a 0us latency, all +- * levels m (m >= n) need to be disabled. We make sure to +- * sanitize the values out of the punit to satisfy this +- * requirement. ++ * to add 2us to the various latency levels we retrieve from the ++ * punit when level 0 response data us 0us. + */ +- wm[0] += 2; +- for (level = 1; level <= max_level; level++) +- if (wm[level] != 0) ++ if (wm[0] == 0) { ++ wm[0] += 2; ++ for (level = 1; level <= max_level; level++) { ++ if (wm[level] == 0) ++ break; + wm[level] += 2; +- else { +- for (i = level + 1; i <= max_level; i++) +- wm[i] = 0; +- +- break; + } ++ } ++ + } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + uint64_t sskpd = I915_READ64(MCH_SSKPD); + diff --git a/queue-4.4/series b/queue-4.4/series index 23d8a6d20c2..140f7480297 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -10,3 +10,4 @@ drm-radeon-si-dpm-fix-phase-shedding-setup.patch drm-radeon-change-vblank_time-s-calculation-method-to-reduce-computational-error.patch drm-vmwgfx-limit-the-user-space-command-buffer-size.patch xenbus-don-t-look-up-transaction-ids-for-ordinary-writes.patch +drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch