From: Richard Henderson Date: Thu, 20 Dec 2012 18:05:03 +0000 (-0800) Subject: s390: Add mode attribute for mode bitsize X-Git-Tag: releases/gcc-4.8.0~1288 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=2542ef057b0a9c35308e7eee2e5fbddac7c67a0c;p=thirdparty%2Fgcc.git s390: Add mode attribute for mode bitsize * config/s390/s390.md (bitsize): New mode attr. (*extzv, *extzv, *insv_zEC12, *insv_z10): Use it. (extend2, zero_extendsi2): Likewise. (zero_extenddi2, fixuns_trunc2): Likewise. Co-Authored-By: Andreas Krebbel From-SVN: r194643 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7972aa133321..3efc06806556 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -16,6 +16,11 @@ (*anddi3_cconly, *anddi3): Likewise. (*andsi3, *andsi3_cconly, *andsi3_zarch): Likewise. + * config/s390/s390.md (bitsize): New mode attr. + (*extzv, *extzv, *insv_zEC12, *insv_z10): Use it. + (extend2, zero_extendsi2): Likewise. + (zero_extenddi2, fixuns_trunc2): Likewise. + 2012-12-20 Thomas Schwinge PR bootstrap/55202 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 0887eae21958..d7adde5e724c 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -531,6 +531,9 @@ (define_mode_attr bfstart [(DI "s") (SI "t")]) (define_mode_attr bfend [(DI "e") (SI "f")]) +;; In place of GET_MODE_BITSIZE (mode) +(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) + ;; ;;- Compare instructions. ;; @@ -3326,7 +3329,7 @@ operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], size); - operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize); + operands[2] = GEN_INT ( - bitsize); operands[3] = GEN_INT (mask); }) @@ -3353,7 +3356,7 @@ operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], size); - operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize); + operands[2] = GEN_INT ( - bitsize); operands[3] = GEN_INT (mask); }) @@ -3373,49 +3376,29 @@ FAIL; }) + +; The normal RTL expansion will never generate a zero_extract where +; the location operand isn't word mode. However, we do this in the +; back-end when generating atomic operations. See s390_two_part_insv. (define_insn "*insv_zEC12" [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") - (match_operand 1 "const_int_operand" "I") - (match_operand 2 "const_int_operand" "I")) + (match_operand 1 "const_int_operand" "I") ; size + (match_operand 2 "const_int_operand" "I")) ; pos (match_operand:GPR 3 "nonimmediate_operand" "d"))] "TARGET_ZEC12 - && (INTVAL (operands[1]) + INTVAL (operands[2])) <= - GET_MODE_BITSIZE (mode)" -{ - int start = INTVAL (operands[2]); - int size = INTVAL (operands[1]); - int offset = 64 - GET_MODE_BITSIZE (mode); - - operands[2] = GEN_INT (offset + start); /* start bit position */ - operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ - operands[4] = GEN_INT (GET_MODE_BITSIZE (mode) - - start - size); /* left shift count */ - - return "risbgn\t%0,%3,%b2,%b1,%b4"; -} + && (INTVAL (operands[1]) + INTVAL (operands[2])) <= " + "risbgn\t%0,%3,64-+%2,64-+%2+%1-1,-%2-%1" [(set_attr "op_type" "RIE")]) (define_insn "*insv_z10" [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") - (match_operand 1 "const_int_operand" "I") - (match_operand 2 "const_int_operand" "I")) + (match_operand 1 "const_int_operand" "I") ; size + (match_operand 2 "const_int_operand" "I")) ; pos (match_operand:GPR 3 "nonimmediate_operand" "d")) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10 - && (INTVAL (operands[1]) + INTVAL (operands[2])) <= - GET_MODE_BITSIZE (mode)" -{ - int start = INTVAL (operands[2]); - int size = INTVAL (operands[1]); - int offset = 64 - GET_MODE_BITSIZE (mode); - - operands[2] = GEN_INT (offset + start); /* start bit position */ - operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ - operands[4] = GEN_INT (GET_MODE_BITSIZE (mode) - - start - size); /* left shift count */ - - return "risbg\t%0,%3,%b2,%b1,%b4"; -} + && (INTVAL (operands[1]) + INTVAL (operands[2])) <= " + "risbg\t%0,%3,64-+%2,64-+%2+%1-1,-%2-%1" [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) @@ -3585,8 +3568,7 @@ } else if (!TARGET_EXTIMM) { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE (mode) - - GET_MODE_BITSIZE (mode)); + rtx bitcount = GEN_INT ( - ); operands[1] = gen_lowpart (mode, operands[1]); emit_insn (gen_ashl3 (operands[0], operands[1], bitcount)); @@ -3688,8 +3670,7 @@ { operands[1] = adjust_address (operands[1], BLKmode, 0); set_mem_size (operands[1], GET_MODE_SIZE (QImode)); - operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - - GET_MODE_BITSIZE (QImode)); + operands[2] = GEN_INT ( - BITS_PER_UNIT); }) ; @@ -3800,8 +3781,7 @@ } else if (!TARGET_EXTIMM) { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - - GET_MODE_BITSIZE(mode)); + rtx bitcount = GEN_INT (64 - ); operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); @@ -3818,7 +3798,7 @@ { operands[1] = gen_lowpart (SImode, operands[1]); emit_insn (gen_andsi3 (operands[0], operands[1], - GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1))); + GEN_INT ((1 << ) - 1))); DONE; } }) @@ -4011,8 +3991,8 @@ REAL_VALUE_TYPE cmp, sub; operands[1] = force_reg (mode, operands[1]); - real_2expN (&cmp, GET_MODE_BITSIZE(mode) - 1, mode); - real_2expN (&sub, GET_MODE_BITSIZE(mode), mode); + real_2expN (&cmp, - 1, mode); + real_2expN (&sub, , mode); emit_cmp_and_jump_insns (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, mode), @@ -4727,9 +4707,9 @@ (plus:GPR (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") - || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") - || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) - && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(mode) - 1))" + || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") + /* Avoid INT32_MIN on 32 bit. */ + && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" "@ ahi\t%0,%h2 ahik\t%0,%1,%h2