From: Richard Sandiford Date: Sun, 23 Sep 2007 09:24:21 +0000 (+0000) Subject: mips.h (ISA_HAS_DSP, [...]): New macros. X-Git-Tag: releases/gcc-4.3.0~2436 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=254d164615d2c3c3225626fe7ee6d70802bafe5e;p=thirdparty%2Fgcc.git mips.h (ISA_HAS_DSP, [...]): New macros. gcc/ * config/mips/mips.h (ISA_HAS_DSP, ISA_HAS_DSPR2): New macros. * config/mips/mips.c (mips_set_mips16_mode): Don't clear the DSP flags for MIPS16. (override_options): Check TARGET_HARD_FLOAT_ABI instead of TARGET_HARD_FLOAT when testing whether -mpaired-single is supported. (mips_conditional_register_usage): Check ISA_HAS_DSP instead of TARGET_DSP. * config/mips/constraints.md (ka): Check ISA_HAS_DSPR2 instead of TARGET_DSPR2. * config/mips/mips.md (ANYF): Require TARGET_HARD_FLOAT for V2SF. (mulv2sf3, movv2sf, movv2sf_hardfloat_64bit): Require TARGET_HARD_FLOAT. (mulsidi3_32bit_internal, msubsidi4, maddsidi4): Check ISA_HAS_DSPR2 instead of TARGET_HAS_DSPR2. * config/mips/mips-dsp.md: Use ISA_HAS_DSP instead of TARGET_HAS_DSP throughout. * config/mips/mips-dspr2.md: Likewise ISA_HAS_DSPR2 and TARGET_HAS_DSPR2. * config/mips/mips-fixed.md: Use ISA_HAS_DSP and ISA_HAS_DSPR2 instead of TARGET_HAS_DSP and TARGET_HAS_DSPR2. * config/mips/mips-ps-3d.md: Add TARGET_HARD_FLOAT to V2SF patterns. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_nomips16): New procedure. * lib/fortran-torture.exp: Check nomips16 as well as mpaired_single for mipsisa64*-*-*. * gcc.dg/vect/vect.exp: Likewise. * g++.dg/vect/vect.exp: Likewise. * gcc.target/mips/mips.exp (setup_mips_tests): Don't set mips_mips16. (dg-mips-options): Don't skip -march* and -mips* tests for -mips16. * gcc.target/mips/branch-cost-1.c (foo): Add NOMIPS16. * gcc.target/mips/branch-cost-2.c (foo): Likewise. * gcc.target/mips/clear-cache-1.c (f): Likewise. * gcc.target/mips/dpaq_sa_l_w.c (f1, f2, f3): Likewise. * gcc.target/mips/dpsq_sa_l_w.c (f1, f2, f3): Likewise. * gcc.target/mips/fix-vr4130-1.c (foo): Likewise. * gcc.target/mips/fix-vr4130-2.c (foo): Likewise. * gcc.target/mips/fix-vr4130-3.c (foo): Likewise. * gcc.target/mips/fix-vr4130-4.c (foo): Likewise. * gcc.target/mips/fixed-scalar-type.c (test1, test2, test3, test4) (test5, test6, test7, test8, test9, test10, test11, test12, test13) (test14, test15, test16, test17, test18): Likewise. * gcc.target/mips/fixed-vector-type.c (test1, test2, test3, test4) (test5, test6, test7, test8, test9, test10, test11, test12, test13) (test14, test15, test16, test17, test18, test19, test20, test21) (test22): Likewise. * gcc.target/mips/madd-1.c (f1, f2, f3): Likewise. * gcc.target/mips/madd-2.c (f1, f2, f3): Likewise. * gcc.target/mips/madd-4.c (f1, f2, f3): Likewise. * gcc.target/mips/maddu-1.c (f1, f2, f3): Likewise. * gcc.target/mips/maddu-2.c (f1, f2, f3): Likewise. * gcc.target/mips/maddu-4.c (f1, f2, f3): Likewise. * gcc.target/mips/mips-3d-1.c (main): Likewise. * gcc.target/mips/mips-3d-2.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-3d-3.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31, test32, test33, test34, test35, test36) (test37, test38, test39, test40, test41, test42, test43, test44) (test45, test46, test47, test48, test49, test50, test51, test52) (test53, test54, test55, test56, test57, test58, test59, test60) (test61, test62, test63): Likewise. * gcc.target/mips/mips-3d-4.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-3d-5.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-3d-6.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15): Likewise. * gcc.target/mips/mips-3d-7.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15): Likewise. * gcc.target/mips/mips-3d-8.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-3d-9.c (matrix_multiply2, matrix_multiply3) (matrix_multiply4: Likewise. * gcc.target/mips/mips-ps-1.c (main): Likewise. * gcc.target/mips/mips-ps-2.c (main): Likewise. * gcc.target/mips/mips-ps-3.c (main): Likewise. * gcc.target/mips/mips-ps-4.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-ps-5.c (main, test0, test1, test2, test3) (test4, test5, test6, test7, test8, test9, test10, test11, test12) (test13, test14, test15, test16, test17, test18, test19, test20) (test21, test22, test23, test24, test25, test26, test27, test28) (test29, test30, test31): Likewise. * gcc.target/mips/mips-ps-5.c (main): Likewise. * gcc.target/mips/mips-ps-6.c (main): Likewise. * gcc.target/mips/mips-ps-type.c (init, move, load, store, add, sub) (neg, mul, madd, msub, nmadd, nmsub, cond_move1, cond_move2): Likewise. * gcc.target/mips/mips32-dsp-type.c (add_v2hi,add_v4qi, sub_v2hi) (sub_v4qi): Likewise. * gcc.target/mips/mips32-dsp.c (test_MIPS_DSP, add_v2q15, add_v4i8) (sub_v2q15, sub_v4i8, test_MIPS_DSP): Likewise. * gcc.target/mips/movcc-1.c (sub1, sub2): Likewise. * gcc.target/mips/movcc-2.c (sub4, sub5): Likewise. * gcc.target/mips/movcc-3.c (sub3, sub6, sub7, sub8, sub9, suba) (subb, subc): Likewise. * gcc.target/mips/msub-1.c (f1, f2): Likewise. * gcc.target/mips/msub-2.c (f1, f2): Likewise. * gcc.target/mips/msub-4.c (f1, f2): Likewise. * gcc.target/mips/msubu-1.c (f1, f2): Likewise. * gcc.target/mips/msubu-2.c (f1, f2): Likewise. * gcc.target/mips/msubu-4.c (f1, f2): Likewise. * gcc.target/mips/nmadd-1.c (sub1, sub2, sub3, sub4): Likewise. * gcc.target/mips/nmadd-2.c (sub1, sub2, sub3, sub4): Likewise. * gcc.target/mips/rsqrt-1.c (foo, bar): Likewise. * gcc.target/mips/rsqrt-2.c (foo, bar): Likewise. * gcc.target/mips/sb1-1.c (divide, recip, squareroot, rsqrt): Likewise. * gcc.target/mips/vr-mult-1.c (f1, f2): Likewise. * gcc.target/mips/vr-mult-2.c (f1, f2): Likewise. From-SVN: r128683 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2de9c65b9ad4..350b9bab73de 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,28 @@ +2007-09-23 Richard Sandiford + + * config/mips/mips.h (ISA_HAS_DSP, ISA_HAS_DSPR2): New macros. + * config/mips/mips.c (mips_set_mips16_mode): Don't clear the DSP + flags for MIPS16. + (override_options): Check TARGET_HARD_FLOAT_ABI instead of + TARGET_HARD_FLOAT when testing whether -mpaired-single is + supported. + (mips_conditional_register_usage): Check ISA_HAS_DSP instead of + TARGET_DSP. + * config/mips/constraints.md (ka): Check ISA_HAS_DSPR2 instead of + TARGET_DSPR2. + * config/mips/mips.md (ANYF): Require TARGET_HARD_FLOAT for V2SF. + (mulv2sf3, movv2sf, movv2sf_hardfloat_64bit): Require + TARGET_HARD_FLOAT. + (mulsidi3_32bit_internal, msubsidi4, maddsidi4): Check + ISA_HAS_DSPR2 instead of TARGET_HAS_DSPR2. + * config/mips/mips-dsp.md: Use ISA_HAS_DSP instead of TARGET_HAS_DSP + throughout. + * config/mips/mips-dspr2.md: Likewise ISA_HAS_DSPR2 and + TARGET_HAS_DSPR2. + * config/mips/mips-fixed.md: Use ISA_HAS_DSP and ISA_HAS_DSPR2 + instead of TARGET_HAS_DSP and TARGET_HAS_DSPR2. + * config/mips/mips-ps-3d.md: Add TARGET_HARD_FLOAT to V2SF patterns. + 2007-09-22 Jason Merrill PR c++/19407 diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 98e8d6f2faae..53e0189ec947 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -80,7 +80,7 @@ ;; Registers that can be used as the target of multiply-accumulate ;; instructions. The core MIPS32 ISA provides a hi/lo madd, ;; but the DSPr2 version allows any accumulator target. -(define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS") +(define_register_constraint "ka" "ISA_HAS_DSPR2 ? ACC_REGS : MD_REGS") (define_constraint "kf" "@internal" diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md index 60b3a94ee6a5..5e6091a3f0ab 100644 --- a/gcc/config/mips/mips-dsp.md +++ b/gcc/config/mips/mips-dsp.md @@ -7,17 +7,17 @@ (CCDSP_EF_REGNUM 187)]) ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE. -(define_mode_iterator DSP [(SI "TARGET_DSP") - (V2HI "TARGET_DSP") - (V4QI "TARGET_DSP")]) +(define_mode_iterator DSP [(SI "ISA_HAS_DSP") + (V2HI "ISA_HAS_DSP") + (V4QI "ISA_HAS_DSP")]) ;; This mode iterator allows v2hi, v4qi for vector/SIMD data. -(define_mode_iterator DSPV [(V2HI "TARGET_DSP") - (V4QI "TARGET_DSP")]) +(define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP") + (V4QI "ISA_HAS_DSP")]) ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data. -(define_mode_iterator DSPQ [(SI "TARGET_DSP") - (V2HI "TARGET_DSP")]) +(define_mode_iterator DSPQ [(SI "ISA_HAS_DSP") + (V2HI "ISA_HAS_DSP")]) ;; DSP instructions use q for fixed-point data, and u for integer in the infix. (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) @@ -68,7 +68,7 @@ (match_operand:DSPV 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] - "TARGET_DSP" + "ISA_HAS_DSP" "sub.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -81,7 +81,7 @@ UNSPEC_SUBQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] - "TARGET_DSP" + "ISA_HAS_DSP" "sub_s.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -95,7 +95,7 @@ UNSPEC_ADDSC)) (set (reg:CCDSP CCDSP_CA_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] - "TARGET_DSP" + "ISA_HAS_DSP" "addsc\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -110,7 +110,7 @@ UNSPEC_ADDWC)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] - "TARGET_DSP" + "ISA_HAS_DSP" "addwc\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -121,7 +121,7 @@ (unspec:SI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")] UNSPEC_MODSUB))] - "TARGET_DSP" + "ISA_HAS_DSP" "modsub\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -131,7 +131,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_RADDU_W_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" "raddu.w.qb\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -144,7 +144,7 @@ UNSPEC_ABSQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] - "TARGET_DSP" + "ISA_HAS_DSP" "absq_s.\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -155,7 +155,7 @@ (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")] UNSPEC_PRECRQ_QB_PH))] - "TARGET_DSP" + "ISA_HAS_DSP" "precrq.qb.ph\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -165,7 +165,7 @@ (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")] UNSPEC_PRECRQ_PH_W))] - "TARGET_DSP" + "ISA_HAS_DSP" "precrq.ph.w\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -179,7 +179,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_PRECRQ_RS_PH_W))])] - "TARGET_DSP" + "ISA_HAS_DSP" "precrq_rs.ph.w\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -194,7 +194,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_PRECRQU_S_QB_PH))])] - "TARGET_DSP" + "ISA_HAS_DSP" "precrqu_s.qb.ph\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -204,7 +204,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] UNSPEC_PRECEQ_W_PHL))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceq.w.phl\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -213,7 +213,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] UNSPEC_PRECEQ_W_PHR))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceq.w.phr\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -223,7 +223,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEQU_PH_QBL))] - "TARGET_DSP" + "ISA_HAS_DSP" "precequ.ph.qbl\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -232,7 +232,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEQU_PH_QBR))] - "TARGET_DSP" + "ISA_HAS_DSP" "precequ.ph.qbr\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -241,7 +241,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEQU_PH_QBLA))] - "TARGET_DSP" + "ISA_HAS_DSP" "precequ.ph.qbla\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -250,7 +250,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEQU_PH_QBRA))] - "TARGET_DSP" + "ISA_HAS_DSP" "precequ.ph.qbra\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -260,7 +260,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEU_PH_QBL))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceu.ph.qbl\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -269,7 +269,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEU_PH_QBR))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceu.ph.qbr\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -278,7 +278,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEU_PH_QBLA))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceu.ph.qbla\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -287,7 +287,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d") (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] UNSPEC_PRECEU_PH_QBRA))] - "TARGET_DSP" + "ISA_HAS_DSP" "preceu.ph.qbra\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -302,7 +302,7 @@ UNSPEC_SHLL)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -324,7 +324,7 @@ UNSPEC_SHLL_S)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -344,7 +344,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRL_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -363,7 +363,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRA_PH))] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -381,7 +381,7 @@ (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRA_R))] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -406,7 +406,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSP" + "ISA_HAS_DSP" "muleu_s.ph.qbl\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -420,7 +420,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSP" + "ISA_HAS_DSP" "muleu_s.ph.qbr\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -435,7 +435,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSP" + "ISA_HAS_DSP" "mulq_rs.ph\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -450,7 +450,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSP" + "ISA_HAS_DSP" "muleq_s.w.phl\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -464,7 +464,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSP" + "ISA_HAS_DSP" "muleq_s.w.phr\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -476,7 +476,7 @@ (match_operand:V4QI 2 "register_operand" "d") (match_operand:V4QI 3 "register_operand" "d")] UNSPEC_DPAU_H_QBL))] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpau.h.qbl\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -487,7 +487,7 @@ (match_operand:V4QI 2 "register_operand" "d") (match_operand:V4QI 3 "register_operand" "d")] UNSPEC_DPAU_H_QBR))] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpau.h.qbr\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -499,7 +499,7 @@ (match_operand:V4QI 2 "register_operand" "d") (match_operand:V4QI 3 "register_operand" "d")] UNSPEC_DPSU_H_QBL))] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpsu.h.qbl\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -510,7 +510,7 @@ (match_operand:V4QI 2 "register_operand" "d") (match_operand:V4QI 3 "register_operand" "d")] UNSPEC_DPSU_H_QBR))] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpsu.h.qbr\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -526,7 +526,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_S_W_PH))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_s.w.ph\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -542,7 +542,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_S_W_PH))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_s.w.ph\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -558,7 +558,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MULSAQ_S_W_PH))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "mulsaq_s.w.ph\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -574,7 +574,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_SA_L_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_sa.l.w\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -590,7 +590,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_SA_L_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_sa.l.w\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -606,7 +606,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_S_W_PHL))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "maq_s.w.phl\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -621,7 +621,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_S_W_PHR))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "maq_s.w.phr\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -637,7 +637,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_SA_W_PHL))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "maq_sa.w.phl\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -652,7 +652,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_MAQ_SA_W_PHR))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "maq_sa.w.phr\t%q0,%2,%3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -663,7 +663,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_BITREV))] - "TARGET_DSP" + "ISA_HAS_DSP" "bitrev\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -676,7 +676,7 @@ (reg:CCDSP CCDSP_SC_REGNUM) (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_INSV))] - "TARGET_DSP" + "ISA_HAS_DSP" "insv\t%0,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -686,7 +686,7 @@ [(set (match_operand:V4QI 0 "register_operand" "=d,d") (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] UNSPEC_REPL_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" { if (which_alternative == 0) { @@ -703,7 +703,7 @@ [(set (match_operand:V2HI 0 "register_operand" "=d,d") (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] UNSPEC_REPL_PH))] - "TARGET_DSP" + "ISA_HAS_DSP" "@ repl.ph\t%0,%1 replv.ph\t%0,%1" @@ -718,7 +718,7 @@ (match_operand:DSPV 1 "register_operand" "d") (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMP_EQ))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmp.eq.\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -729,7 +729,7 @@ (match_operand:DSPV 1 "register_operand" "d") (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMP_LT))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmp.lt.\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -740,7 +740,7 @@ (match_operand:DSPV 1 "register_operand" "d") (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMP_LE))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmp.le.\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -750,7 +750,7 @@ (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") (match_operand:V4QI 2 "register_operand" "d")] UNSPEC_CMPGU_EQ_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmpgu.eq.qb\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -760,7 +760,7 @@ (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") (match_operand:V4QI 2 "register_operand" "d")] UNSPEC_CMPGU_LT_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmpgu.lt.qb\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -770,7 +770,7 @@ (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") (match_operand:V4QI 2 "register_operand" "d")] UNSPEC_CMPGU_LE_QB))] - "TARGET_DSP" + "ISA_HAS_DSP" "cmpgu.le.qb\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -782,7 +782,7 @@ (match_operand:DSPV 2 "register_operand" "d") (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_PICK))] - "TARGET_DSP" + "ISA_HAS_DSP" "pick.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -793,7 +793,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") (match_operand:V2HI 2 "register_operand" "d")] UNSPEC_PACKRL_PH))] - "TARGET_DSP" + "ISA_HAS_DSP" "packrl.ph\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -808,7 +808,7 @@ UNSPEC_EXTR_W)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -829,7 +829,7 @@ UNSPEC_EXTR_R_W)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -850,7 +850,7 @@ UNSPEC_EXTR_RS_W)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -872,7 +872,7 @@ UNSPEC_EXTR_S_H)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -895,7 +895,7 @@ UNSPEC_EXTP)) (set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -920,7 +920,7 @@ (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) (set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -939,7 +939,7 @@ (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHILO))] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" { if (which_alternative == 0) { @@ -963,7 +963,7 @@ (set (reg:CCDSP CCDSP_PO_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "mthlip\t%2,%q0" [(set_attr "type" "mfhilo") (set_attr "mode" "SI")]) @@ -985,7 +985,7 @@ (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) (set (reg:CCDSP CCDSP_EF_REGNUM) (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] - "TARGET_DSP" + "ISA_HAS_DSP" "wrdsp\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -1001,7 +1001,7 @@ (reg:CCDSP CCDSP_CC_REGNUM) (reg:CCDSP CCDSP_EF_REGNUM)] UNSPEC_RDDSP))] - "TARGET_DSP" + "ISA_HAS_DSP" "rddsp\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -1014,7 +1014,7 @@ "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))))] - "TARGET_DSP" + "ISA_HAS_DSP" "lbux\t%0,%2(%1)" [(set_attr "type" "load") (set_attr "mode" "SI") @@ -1026,7 +1026,7 @@ "register_operand" "d") (match_operand:SI 2 "register_operand" "d")))))] - "TARGET_DSP" + "ISA_HAS_DSP" "lhx\t%0,%2(%1)" [(set_attr "type" "load") (set_attr "mode" "SI") @@ -1036,7 +1036,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d"))))] - "TARGET_DSP" + "ISA_HAS_DSP" "lwx\t%0,%2(%1)" [(set_attr "type" "load") (set_attr "mode" "SI") @@ -1050,7 +1050,7 @@ (match_operand:SI 0 "immediate_operand" "I")) (label_ref (match_operand 1 "" "")) (pc)))] - "TARGET_DSP" + "ISA_HAS_DSP" "%*bposge%0\t%1%/" [(set_attr "type" "branch") (set_attr "mode" "none")]) diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index 201900851778..3cde900b69bd 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -7,7 +7,7 @@ UNSPEC_ABSQ_S_QB)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "absq_s.qb\t%0,%z1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -19,7 +19,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG"))) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addu.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -32,7 +32,7 @@ UNSPEC_ADDU_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addu_s.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -42,7 +42,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_ADDUH_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "adduh.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -52,7 +52,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_ADDUH_R_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "adduh_r.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -63,7 +63,7 @@ (match_operand:SI 2 "reg_or_0_operand" "dJ") (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_APPEND))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) operands[2] = GEN_INT (INTVAL (operands[2]) & 31); @@ -78,7 +78,7 @@ (match_operand:SI 2 "reg_or_0_operand" "dJ") (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_BALIGN))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3) operands[2] = GEN_INT (INTVAL (operands[2]) & 3); @@ -97,7 +97,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_EQ_QB))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "cmpgdu.eq.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -112,7 +112,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_LT_QB))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "cmpgdu.lt.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -127,7 +127,7 @@ (unspec:CCDSP [(match_dup 1) (match_dup 2) (reg:CCDSP CCDSP_CC_REGNUM)] UNSPEC_CMPGDU_LE_QB))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "cmpgdu.le.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -138,7 +138,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPA_W_PH))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpa.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -149,7 +149,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPS_W_PH))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dps.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -160,7 +160,7 @@ (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) (any_extend:DI (match_operand:SI 3 "register_operand"))) (match_operand:DI 1 "register_operand")))] - "TARGET_DSPR2 && !TARGET_64BIT") + "ISA_HAS_DSPR2 && !TARGET_64BIT") (define_expand "mips_msub" [(set (match_operand:DI 0 "register_operand") @@ -168,7 +168,7 @@ (match_operand:DI 1 "register_operand") (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) (any_extend:DI (match_operand:SI 3 "register_operand")))))] - "TARGET_DSPR2 && !TARGET_64BIT") + "ISA_HAS_DSPR2 && !TARGET_64BIT") (define_insn "mulv2hi3" [(parallel @@ -178,7 +178,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "mul.ph\t%0,%1,%2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -192,7 +192,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "mul_s.ph\t%0,%z1,%z2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -206,7 +206,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "mulq_rs.w\t%0,%z1,%z2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -220,7 +220,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "mulq_s.ph\t%0,%z1,%z2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -234,7 +234,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W)) (clobber (match_scratch:DI 3 "=x"))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "mulq_s.w\t%0,%z1,%z2" [(set_attr "type" "imul3") (set_attr "mode" "SI")]) @@ -245,7 +245,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_MULSA_W_PH))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "mulsa.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -255,7 +255,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "mult\t%q0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -265,7 +265,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "multu\t%q0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -275,7 +275,7 @@ (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_PRECR_QB_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "precr.qb.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -286,7 +286,7 @@ (match_operand:SI 2 "reg_or_0_operand" "dJ") (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_PRECR_SRA_PH_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) operands[2] = GEN_INT (INTVAL (operands[2]) & 31); @@ -301,7 +301,7 @@ (match_operand:SI 2 "reg_or_0_operand" "dJ") (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_PRECR_SRA_R_PH_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) operands[2] = GEN_INT (INTVAL (operands[2]) & 31); @@ -316,7 +316,7 @@ (match_operand:SI 2 "reg_or_0_operand" "dJ") (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_PREPEND))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) operands[2] = GEN_INT (INTVAL (operands[2]) & 31); @@ -330,7 +330,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRA_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (which_alternative == 0) { @@ -349,7 +349,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRA_R_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (which_alternative == 0) { @@ -367,7 +367,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG") (match_operand:SI 2 "arith_operand" "I,d")] UNSPEC_SHRL_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" { if (which_alternative == 0) { @@ -388,7 +388,7 @@ UNSPEC_SUBU_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subu.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -401,7 +401,7 @@ UNSPEC_SUBU_S_PH)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subu_s.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -411,7 +411,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBUH_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subuh.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -421,7 +421,7 @@ (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBUH_R_QB))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subuh_r.qb\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -431,7 +431,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_ADDQH_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addqh.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -441,7 +441,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_ADDQH_R_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addqh_r.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -451,7 +451,7 @@ (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_ADDQH_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addqh.w\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -461,7 +461,7 @@ (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_ADDQH_R_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "addqh_r.w\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -471,7 +471,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBQH_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subqh.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -481,7 +481,7 @@ (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] UNSPEC_SUBQH_R_PH))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subqh_r.ph\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -491,7 +491,7 @@ (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_SUBQH_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subqh.w\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -501,7 +501,7 @@ (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "reg_or_0_operand" "dJ")] UNSPEC_SUBQH_R_W))] - "TARGET_DSPR2" + "ISA_HAS_DSPR2" "subqh_r.w\t%0,%z1,%z2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -512,7 +512,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPAX_W_PH))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpax.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -523,7 +523,7 @@ (match_operand:V2HI 2 "reg_or_0_operand" "dYG") (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] UNSPEC_DPSX_W_PH))] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsx.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -538,7 +538,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQX_S_W_PH))])] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpaqx_s.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -553,7 +553,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQX_SA_W_PH))])] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpaqx_sa.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -568,7 +568,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQX_S_W_PH))])] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsqx_s.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -583,7 +583,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQX_SA_W_PH))])] - "TARGET_DSPR2 && !TARGET_64BIT" + "ISA_HAS_DSPR2 && !TARGET_64BIT" "dpsqx_sa.w.ph\t%q0,%z2,%z3" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) diff --git a/gcc/config/mips/mips-fixed.md b/gcc/config/mips/mips-fixed.md index 3305be8b35a1..758df26c7a63 100644 --- a/gcc/config/mips/mips-fixed.md +++ b/gcc/config/mips/mips-fixed.md @@ -13,15 +13,15 @@ (V2HQ "ph") (V2HA "ph")]) ;; For unsigned add/sub with saturation -(define_mode_iterator UADDSUB [(UQQ "TARGET_DSP") (UHQ "TARGET_DSPR2") - (UHA "TARGET_DSPR2") (V4UQQ "TARGET_DSP") - (V2UHQ "TARGET_DSPR2") (V2UHA "TARGET_DSPR2")]) +(define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2") + (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP") + (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")]) (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph") (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")]) ;; For signed multiplication with saturation -(define_mode_iterator MULQ [(V2HQ "TARGET_DSP") (HQ "TARGET_DSP") - (SQ "TARGET_DSPR2")]) +(define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP") + (SQ "ISA_HAS_DSPR2")]) (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")]) (define_insn "add3" @@ -52,7 +52,7 @@ (match_operand:ADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] - "TARGET_DSP" + "ISA_HAS_DSP" "addq_s.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "")]) @@ -85,7 +85,7 @@ (match_operand:ADDSUB 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] - "TARGET_DSP" + "ISA_HAS_DSP" "subq_s.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "")]) @@ -115,7 +115,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPAQ_SA_L_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpaq_sa.l.w\t%q0,%1,%2" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) @@ -132,7 +132,7 @@ (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_DPSQ_SA_L_W))])] - "TARGET_DSP && !TARGET_64BIT" + "ISA_HAS_DSP && !TARGET_64BIT" "dpsq_sa.l.w\t%q0,%1,%2" [(set_attr "type" "imadd") (set_attr "mode" "SI")]) diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md index 36cc4c1658fa..63ec16b3de5e 100644 --- a/gcc/config/mips/mips-ps-3d.md +++ b/gcc/config/mips/mips-ps-3d.md @@ -25,7 +25,7 @@ (const_int 0)]) (match_operand:V2SF 2 "register_operand" "f,0") (match_operand:V2SF 3 "register_operand" "0,f")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "@ mov%T4.ps\t%0,%2,%1 mov%t4.ps\t%0,%3,%1" @@ -38,7 +38,7 @@ (match_operand:V2SF 2 "register_operand" "0,f") (match_operand:CCV2 3 "register_operand" "z,z")] UNSPEC_MOVE_TF_PS))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "@ movt.ps\t%0,%1,%3 movf.ps\t%0,%2,%3" @@ -51,7 +51,7 @@ (if_then_else:V2SF (match_dup 5) (match_operand:V2SF 2 "register_operand") (match_operand:V2SF 3 "register_operand")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { /* We can only support MOVN.PS and MOVZ.PS. NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and @@ -72,7 +72,7 @@ (match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f") (const_int 2)))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "pul.ps\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) @@ -86,7 +86,7 @@ (parallel [(const_int 1) (const_int 0)])) (const_int 2)))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "puu.ps\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) @@ -100,7 +100,7 @@ (const_int 0)])) (match_operand:V2SF 2 "register_operand" "f") (const_int 2)))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "pll.ps\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) @@ -116,7 +116,7 @@ (parallel [(const_int 1) (const_int 0)])) (const_int 2)))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "plu.ps\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) @@ -125,7 +125,7 @@ (define_expand "vec_initv2sf" [(match_operand:V2SF 0 "register_operand") (match_operand:V2SF 1 "")] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0)); rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1)); @@ -138,7 +138,7 @@ (vec_concat:V2SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { if (BYTES_BIG_ENDIAN) return "cvt.ps.s\t%0,%1,%2"; @@ -157,7 +157,7 @@ (vec_select:SF (match_operand:V2SF 1 "register_operand" "f") (parallel [(match_operand 2 "const_0_or_1_operand" "")])))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) return "cvt.s.pu\t%0,%1"; @@ -174,7 +174,7 @@ [(match_operand:V2SF 0 "register_operand") (match_operand:SF 1 "register_operand") (match_operand 2 "const_0_or_1_operand")] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { rtx temp; @@ -194,7 +194,7 @@ [(match_operand:V2SF 0 "register_operand") (match_operand:SF 1 "register_operand") (match_operand:SF 2 "register_operand")] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1], @@ -210,7 +210,7 @@ [(set (match_operand:SF 0 "register_operand") (vec_select:SF (match_operand:V2SF 1 "register_operand") (parallel [(match_dup 2)])))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); }) ; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point @@ -218,7 +218,7 @@ [(set (match_operand:SF 0 "register_operand") (vec_select:SF (match_operand:V2SF 1 "register_operand") (parallel [(match_dup 2)])))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); }) ; alnv.ps - Floating Point Align Variable @@ -228,7 +228,7 @@ (match_operand:V2SF 2 "register_operand" "f") (match_operand:SI 3 "register_operand" "d")] UNSPEC_ALNV_PS))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "alnv.ps\t%0,%1,%2,%3" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) @@ -239,7 +239,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f")] UNSPEC_ADDR_PS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "addr.ps\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "SF")]) @@ -249,7 +249,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=f") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] UNSPEC_CVT_PW_PS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "cvt.pw.ps\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -259,7 +259,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=f") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] UNSPEC_CVT_PS_PW))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "cvt.ps.pw\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -270,7 +270,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f")] UNSPEC_MULR_PS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "mulr.ps\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "SF")]) @@ -280,7 +280,7 @@ [(set (match_operand:V2SF 0 "register_operand") (unspec:V2SF [(match_operand:V2SF 1 "register_operand")] UNSPEC_ABS_PS))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { /* If we can ignore NaNs, this operation is equivalent to the rtl ABS code. */ @@ -295,7 +295,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=f") (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] UNSPEC_ABS_PS))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "abs.ps\t%0,%1" [(set_attr "type" "fabs") (set_attr "mode" "SF")]) @@ -310,7 +310,7 @@ (match_operand:SCALARF 2 "register_operand" "f") (match_operand 3 "const_int_operand" "")] UNSPEC_CABS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "cabs.%Y3.\t%0,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) @@ -328,7 +328,7 @@ (match_operand:V2SF 4 "register_operand" "f") (match_operand 5 "const_int_operand" "")] UNSPEC_C))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "#" "&& reload_completed" [(set (match_dup 6) @@ -357,7 +357,7 @@ (match_operand:V2SF 4 "register_operand" "f") (match_operand 5 "const_int_operand" "")] UNSPEC_CABS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "#" "&& reload_completed" [(set (match_dup 6) @@ -389,7 +389,7 @@ (match_operand:V2SF 2 "register_operand" "f") (match_operand 3 "const_int_operand" "")] UNSPEC_C))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "c.%Y3.ps\t%0,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) @@ -400,7 +400,7 @@ (match_operand:V2SF 2 "register_operand" "f") (match_operand 3 "const_int_operand" "")] UNSPEC_CABS))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "cabs.%Y3.ps\t%0,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) @@ -416,7 +416,7 @@ [(fcond (match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f"))] UNSPEC_SCC))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "c..ps\t%0,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) @@ -427,7 +427,7 @@ [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f"))] UNSPEC_SCC))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "c..ps\t%0,%2,%1" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) @@ -443,7 +443,7 @@ (const_int 0)) (label_ref (match_operand 1 "" "")) (pc)))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "%*bc1any4t\t%0,%1%/" [(set_attr "type" "branch") (set_attr "mode" "none")]) @@ -455,7 +455,7 @@ (const_int -1)) (label_ref (match_operand 1 "" "")) (pc)))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "%*bc1any4f\t%0,%1%/" [(set_attr "type" "branch") (set_attr "mode" "none")]) @@ -467,7 +467,7 @@ (const_int 0)) (label_ref (match_operand 1 "" "")) (pc)))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "%*bc1any2t\t%0,%1%/" [(set_attr "type" "branch") (set_attr "mode" "none")]) @@ -479,7 +479,7 @@ (const_int -1)) (label_ref (match_operand 1 "" "")) (pc)))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "%*bc1any2f\t%0,%1%/" [(set_attr "type" "branch") (set_attr "mode" "none")]) @@ -545,7 +545,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RSQRT1))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "rsqrt1.\t%0,%1" [(set_attr "type" "frsqrt1") (set_attr "mode" "")]) @@ -555,7 +555,7 @@ (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") (match_operand:ANYF 2 "register_operand" "f")] UNSPEC_RSQRT2))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "rsqrt2.\t%0,%1,%2" [(set_attr "type" "frsqrt2") (set_attr "mode" "")]) @@ -564,7 +564,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_RECIP1))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "recip1.\t%0,%1" [(set_attr "type" "frdiv1") (set_attr "mode" "")]) @@ -574,7 +574,7 @@ (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") (match_operand:ANYF 2 "register_operand" "f")] UNSPEC_RECIP2))] - "TARGET_MIPS3D" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "recip2.\t%0,%1,%2" [(set_attr "type" "frdiv2") (set_attr "mode" "")]) @@ -587,7 +587,7 @@ (match_operand:V2SF 5 "register_operand")]) (match_operand:V2SF 1 "register_operand") (match_operand:V2SF 2 "register_operand")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { mips_expand_vcondv2sf (operands[0], operands[1], operands[2], GET_CODE (operands[3]), operands[4], operands[5]); @@ -598,7 +598,7 @@ [(set (match_operand:V2SF 0 "register_operand") (smin:V2SF (match_operand:V2SF 1 "register_operand") (match_operand:V2SF 2 "register_operand")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { mips_expand_vcondv2sf (operands[0], operands[1], operands[2], LE, operands[1], operands[2]); @@ -609,7 +609,7 @@ [(set (match_operand:V2SF 0 "register_operand") (smax:V2SF (match_operand:V2SF 1 "register_operand") (match_operand:V2SF 2 "register_operand")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { mips_expand_vcondv2sf (operands[0], operands[1], operands[2], LE, operands[2], operands[1]); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index f2c8ba9fb836..1d72056b2491 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -5696,10 +5696,6 @@ mips_set_mips16_mode (int mips16_p) we use a %gprel() operator. */ target_flags &= ~MASK_EXPLICIT_RELOCS; - /* Silently disable DSP extensions. */ - target_flags &= ~MASK_DSP; - target_flags &= ~MASK_DSPR2; - /* Experiments suggest we get the best overall results from using the range of an unextended lw or sw. Code that makes heavy use of byte or short accesses can do better with ranges of 0...31 @@ -6151,8 +6147,8 @@ override_options (void) target_flags |= MASK_PAIRED_SINGLE_FLOAT; /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 - and TARGET_HARD_FLOAT are both true. */ - if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT)) + and TARGET_HARD_FLOAT_ABI are both true. */ + if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float"); /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is @@ -6351,7 +6347,7 @@ mips_swap_registers (unsigned int i) void mips_conditional_register_usage (void) { - if (!TARGET_DSP) + if (!ISA_HAS_DSP) { int regno; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index d38bba8a63df..169779ce1ee2 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -879,6 +879,12 @@ extern enum mips_llsc_setting mips_llsc; /* ISA has lwxs instruction (load w/scaled index address. */ #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16) +/* The DSP ASE is available. */ +#define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) + +/* Revision 2 of the DSP ASE is available. */ +#define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) + /* True if the result of a load is not available to the next instruction. A nop will then be needed between instructions like "lw $4,..." and "addiu $4,$4,1". */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index efd57c94d5de..92d5ab269f39 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -492,7 +492,7 @@ ;; floating-point mode is allowed. (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT") - (V2SF "TARGET_PAIRED_SINGLE_FLOAT")]) + (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) ;; Like ANYF, but only applies to scalar modes. (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT") @@ -1035,7 +1035,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=f") (mult:V2SF (match_operand:V2SF 1 "register_operand" "f") (match_operand:V2SF 2 "register_operand" "f")))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" "mul.ps\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "SF")]) @@ -1581,7 +1581,7 @@ [(set (match_operand:DI 0 "register_operand" "=x") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] - "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2" + "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2" "mult\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -1678,9 +1678,9 @@ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] - "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)" + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)" { - if (TARGET_DSPR2) + if (ISA_HAS_DSPR2) return "msub\t%q0,%1,%2"; else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) return "msub\t%1,%2"; @@ -1797,12 +1797,12 @@ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) (match_operand:DI 3 "register_operand" "0")))] - "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2) + "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2) && !TARGET_64BIT" { if (TARGET_MAD) return "mad\t%1,%2"; - else if (TARGET_DSPR2) + else if (ISA_HAS_DSPR2) return "madd\t%q0,%1,%2"; else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) return "madd\t%1,%2"; @@ -4043,7 +4043,7 @@ (define_expand "movv2sf" [(set (match_operand:V2SF 0) (match_operand:V2SF 1))] - "TARGET_PAIRED_SINGLE_FLOAT" + "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { if (mips_legitimize_move (V2SFmode, operands[0], operands[1])) DONE; @@ -4052,8 +4052,9 @@ (define_insn "movv2sf_hardfloat_64bit" [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] - "TARGET_PAIRED_SINGLE_FLOAT + "TARGET_HARD_FLOAT && TARGET_64BIT + && TARGET_PAIRED_SINGLE_FLOAT && (register_operand (operands[0], V2SFmode) || reg_or_0_operand (operands[1], V2SFmode))" { return mips_output_move (operands[0], operands[1]); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0dd4f60088c2..21df8be4eb5b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,112 @@ +2007-09-23 Richard Sandiford + + * lib/target-supports.exp (check_effective_target_nomips16): New + procedure. + * lib/fortran-torture.exp: Check nomips16 as well as mpaired_single + for mipsisa64*-*-*. + * gcc.dg/vect/vect.exp: Likewise. + * g++.dg/vect/vect.exp: Likewise. + * gcc.target/mips/mips.exp (setup_mips_tests): Don't set mips_mips16. + (dg-mips-options): Don't skip -march* and -mips* tests for -mips16. + * gcc.target/mips/branch-cost-1.c (foo): Add NOMIPS16. + * gcc.target/mips/branch-cost-2.c (foo): Likewise. + * gcc.target/mips/clear-cache-1.c (f): Likewise. + * gcc.target/mips/dpaq_sa_l_w.c (f1, f2, f3): Likewise. + * gcc.target/mips/dpsq_sa_l_w.c (f1, f2, f3): Likewise. + * gcc.target/mips/fix-vr4130-1.c (foo): Likewise. + * gcc.target/mips/fix-vr4130-2.c (foo): Likewise. + * gcc.target/mips/fix-vr4130-3.c (foo): Likewise. + * gcc.target/mips/fix-vr4130-4.c (foo): Likewise. + * gcc.target/mips/fixed-scalar-type.c (test1, test2, test3, test4) + (test5, test6, test7, test8, test9, test10, test11, test12, test13) + (test14, test15, test16, test17, test18): Likewise. + * gcc.target/mips/fixed-vector-type.c (test1, test2, test3, test4) + (test5, test6, test7, test8, test9, test10, test11, test12, test13) + (test14, test15, test16, test17, test18, test19, test20, test21) + (test22): Likewise. + * gcc.target/mips/madd-1.c (f1, f2, f3): Likewise. + * gcc.target/mips/madd-2.c (f1, f2, f3): Likewise. + * gcc.target/mips/madd-4.c (f1, f2, f3): Likewise. + * gcc.target/mips/maddu-1.c (f1, f2, f3): Likewise. + * gcc.target/mips/maddu-2.c (f1, f2, f3): Likewise. + * gcc.target/mips/maddu-4.c (f1, f2, f3): Likewise. + * gcc.target/mips/mips-3d-1.c (main): Likewise. + * gcc.target/mips/mips-3d-2.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-3d-3.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31, test32, test33, test34, test35, test36) + (test37, test38, test39, test40, test41, test42, test43, test44) + (test45, test46, test47, test48, test49, test50, test51, test52) + (test53, test54, test55, test56, test57, test58, test59, test60) + (test61, test62, test63): Likewise. + * gcc.target/mips/mips-3d-4.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-3d-5.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-3d-6.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15): Likewise. + * gcc.target/mips/mips-3d-7.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15): Likewise. + * gcc.target/mips/mips-3d-8.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-3d-9.c (matrix_multiply2, matrix_multiply3) + (matrix_multiply4: Likewise. + * gcc.target/mips/mips-ps-1.c (main): Likewise. + * gcc.target/mips/mips-ps-2.c (main): Likewise. + * gcc.target/mips/mips-ps-3.c (main): Likewise. + * gcc.target/mips/mips-ps-4.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-ps-5.c (main, test0, test1, test2, test3) + (test4, test5, test6, test7, test8, test9, test10, test11, test12) + (test13, test14, test15, test16, test17, test18, test19, test20) + (test21, test22, test23, test24, test25, test26, test27, test28) + (test29, test30, test31): Likewise. + * gcc.target/mips/mips-ps-5.c (main): Likewise. + * gcc.target/mips/mips-ps-6.c (main): Likewise. + * gcc.target/mips/mips-ps-type.c (init, move, load, store, add, sub) + (neg, mul, madd, msub, nmadd, nmsub, cond_move1, cond_move2): Likewise. + * gcc.target/mips/mips32-dsp-type.c (add_v2hi,add_v4qi, sub_v2hi) + (sub_v4qi): Likewise. + * gcc.target/mips/mips32-dsp.c (test_MIPS_DSP, add_v2q15, add_v4i8) + (sub_v2q15, sub_v4i8, test_MIPS_DSP): Likewise. + * gcc.target/mips/movcc-1.c (sub1, sub2): Likewise. + * gcc.target/mips/movcc-2.c (sub4, sub5): Likewise. + * gcc.target/mips/movcc-3.c (sub3, sub6, sub7, sub8, sub9, suba) + (subb, subc): Likewise. + * gcc.target/mips/msub-1.c (f1, f2): Likewise. + * gcc.target/mips/msub-2.c (f1, f2): Likewise. + * gcc.target/mips/msub-4.c (f1, f2): Likewise. + * gcc.target/mips/msubu-1.c (f1, f2): Likewise. + * gcc.target/mips/msubu-2.c (f1, f2): Likewise. + * gcc.target/mips/msubu-4.c (f1, f2): Likewise. + * gcc.target/mips/nmadd-1.c (sub1, sub2, sub3, sub4): Likewise. + * gcc.target/mips/nmadd-2.c (sub1, sub2, sub3, sub4): Likewise. + * gcc.target/mips/rsqrt-1.c (foo, bar): Likewise. + * gcc.target/mips/rsqrt-2.c (foo, bar): Likewise. + * gcc.target/mips/sb1-1.c (divide, recip, squareroot, rsqrt): Likewise. + * gcc.target/mips/vr-mult-1.c (f1, f2): Likewise. + * gcc.target/mips/vr-mult-2.c (f1, f2): Likewise. + 2007-09-22 Richard Sandiford * lib/target-supports.exp (add_options_for_mips16_attribute) diff --git a/gcc/testsuite/g++.dg/vect/vect.exp b/gcc/testsuite/g++.dg/vect/vect.exp index 29ab4dfca455..1bf6d48f3206 100644 --- a/gcc/testsuite/g++.dg/vect/vect.exp +++ b/gcc/testsuite/g++.dg/vect/vect.exp @@ -67,7 +67,8 @@ if [istarget "powerpc*-*-*"] { lappend DEFAULT_VECTCFLAGS "-msse2" set dg-do-what-default run } elseif { [istarget "mipsisa64*-*-*"] - && [check_effective_target_mpaired_single] } { + && [check_effective_target_mpaired_single] + && [check_effective_target_nomips16] } { lappend DEFAULT_VECTCFLAGS "-mpaired-single" set dg-do-what-default run } elseif [istarget "sparc*-*-*"] { diff --git a/gcc/testsuite/gcc.dg/vect/vect.exp b/gcc/testsuite/gcc.dg/vect/vect.exp index e9be793621e9..e9103328a188 100644 --- a/gcc/testsuite/gcc.dg/vect/vect.exp +++ b/gcc/testsuite/gcc.dg/vect/vect.exp @@ -58,7 +58,8 @@ if [istarget "powerpc*-*-*"] { lappend DEFAULT_VECTCFLAGS "-msse2" set dg-do-what-default run } elseif { [istarget "mipsisa64*-*-*"] - && [check_effective_target_mpaired_single] } { + && [check_effective_target_mpaired_single] + && [check_effective_target_nomips16] } { lappend DEFAULT_VECTCFLAGS "-mpaired-single" set dg-do-what-default run } elseif [istarget "sparc*-*-*"] { diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc/testsuite/gcc.target/mips/branch-cost-1.c index 3b2c80d990ae..8048f37459dd 100644 --- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c +++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c @@ -1,5 +1,5 @@ /* { dg-mips-options "-mbranch-cost=1 -mips64 -O2" } */ -int +NOMIPS16 int foo (int x, int y, int z, int k) { return x == k ? x + y : z - x; diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-2.c b/gcc/testsuite/gcc.target/mips/branch-cost-2.c index 356def21ebee..d4dc8fe1bba9 100644 --- a/gcc/testsuite/gcc.target/mips/branch-cost-2.c +++ b/gcc/testsuite/gcc.target/mips/branch-cost-2.c @@ -1,5 +1,5 @@ /* { dg-mips-options "-mbranch-cost=10 -mips64 -O2" } */ -int +NOMIPS16 int foo (int x, int y, int z, int k) { return x == k ? x + y : z - x; diff --git a/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc/testsuite/gcc.target/mips/clear-cache-1.c index ece1f50daf6f..d6e60c251ff3 100644 --- a/gcc/testsuite/gcc.target/mips/clear-cache-1.c +++ b/gcc/testsuite/gcc.target/mips/clear-cache-1.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler "jr.hb" } } */ /* { dg-final { scan-assembler-not "_flush_cache" } } */ -void f() +NOMIPS16 void f() { int size = 40; char *memory = __builtin_alloca(size); diff --git a/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c b/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c index 2565e1732901..1197fa92a273 100644 --- a/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c +++ b/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c @@ -2,19 +2,19 @@ /* { dg-mips-options "-O2 -mips32r2 -mdsp" } */ /* { dg-final { scan-assembler-times "\tdpaq_sa.l.w\t\\\$ac" 3 } } */ -_Sat long long _Fract +NOMIPS16 _Sat long long _Fract f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) { return (_Sat long long _Fract) x * y + z; } -_Sat long long _Fract +NOMIPS16 _Sat long long _Fract f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) { return z + (_Sat long long _Fract) y * x; } -_Sat long long _Fract +NOMIPS16 _Sat long long _Fract f3 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) { _Sat long long _Fract t = (_Sat long long _Fract) x * y; diff --git a/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c b/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c index f418a13bf5e6..42935bb02150 100644 --- a/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c +++ b/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c @@ -2,13 +2,13 @@ /* { dg-mips-options "-O2 -mips32r2 -mdsp" } */ /* { dg-final { scan-assembler-times "\tdpsq_sa.l.w\t\\\$ac" 2 } } */ -_Sat long long _Fract +NOMIPS16 _Sat long long _Fract f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) { return z - (_Sat long long _Fract) x * y; } -_Sat long long _Fract +NOMIPS16 _Sat long long _Fract f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z) { _Sat long long _Fract t = (_Sat long long _Fract) x * y; diff --git a/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c b/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c index 1ddf547f7029..27ef5ef06ebb 100644 --- a/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c +++ b/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */ -int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; } +NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; } /* { dg-final { scan-assembler "\tmacchi\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c b/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c index 633eae691e66..aaeba4f2836f 100644 --- a/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c +++ b/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */ -int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; } +NOMIPS16 int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; } /* { dg-final { scan-assembler "\tmacc\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c b/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c index 58f07b576bb1..2f4f48689f6d 100644 --- a/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c +++ b/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c @@ -1,4 +1,10 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ -long long foo (void) { long long r; asm ("# foo" : "=h" (r)); return r; } +NOMIPS16 long long +foo (void) +{ + long long r; + asm ("# foo" : "=h" (r)); + return r; +} /* { dg-final { scan-assembler "\tdmacchi\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c b/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c index 64752a8dcfe8..91b883d46b5e 100644 --- a/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c +++ b/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c @@ -1,4 +1,10 @@ /* { dg-do compile } */ /* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */ -long long foo (void) { long long r; asm ("# foo" : "=l" (r)); return r; } +NOMIPS16 long long +foo (void) +{ + long long r; + asm ("# foo" : "=l" (r)); + return r; +} /* { dg-final { scan-assembler "\tdmacc\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c b/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c index 4455d3d693cc..ff4e975618cb 100644 --- a/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c +++ b/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c @@ -83,7 +83,7 @@ long _Fract non_sat_test13 (long _Fract a, long _Fract b) } unsigned short _Fract non_sat_test14 (unsigned short _Fract a, - unsigned short _Fract b) + unsigned short _Fract b) { return a - b; } @@ -94,7 +94,7 @@ unsigned _Fract non_sat_test15 (unsigned _Fract a, unsigned _Fract b) } unsigned long _Fract non_sat_test16 (unsigned long _Fract a, - unsigned long _Fract b) + unsigned long _Fract b) { return a - b; } @@ -110,7 +110,7 @@ _Accum non_sat_test18 (_Accum a, _Accum b) } unsigned short _Accum non_sat_test19 (unsigned short _Accum a, - unsigned short _Accum b) + unsigned short _Accum b) { return a - b; } @@ -120,96 +120,98 @@ unsigned _Accum non_sat_test20 (unsigned _Accum a, unsigned _Accum b) return a - b; } -_Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a, - _Sat unsigned short _Fract b) +NOMIPS16 _Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a, + _Sat unsigned short _Fract b) { return a + b; } -_Sat unsigned _Fract test2 (_Sat unsigned _Fract a, _Sat unsigned _Fract b) +NOMIPS16 _Sat unsigned _Fract test2 (_Sat unsigned _Fract a, + _Sat unsigned _Fract b) { return a + b; } -_Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a, - _Sat unsigned short _Accum b) +NOMIPS16 _Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a, + _Sat unsigned short _Accum b) { return a + b; } -_Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b) +NOMIPS16 _Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b) { return a + b; } -_Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b) +NOMIPS16 _Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b) { return a + b; } -_Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b) +NOMIPS16 _Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b) { return a + b; } -_Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b) +NOMIPS16 _Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b) { return a + b; } -_Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a, - _Sat unsigned short _Fract b) +NOMIPS16 _Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a, + _Sat unsigned short _Fract b) { return a - b; } -_Sat unsigned _Fract test9 (_Sat unsigned _Fract a, _Sat unsigned _Fract b) +NOMIPS16 _Sat unsigned _Fract test9 (_Sat unsigned _Fract a, + _Sat unsigned _Fract b) { return a - b; } -_Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a, - _Sat unsigned short _Accum b) +NOMIPS16 _Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a, + _Sat unsigned short _Accum b) { return a - b; } -_Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b) +NOMIPS16 _Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b) { return a - b; } -_Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b) +NOMIPS16 _Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b) { return a - b; } -_Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b) +NOMIPS16 _Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b) { return a - b; } -_Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b) +NOMIPS16 _Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b) { return a - b; } -_Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b) +NOMIPS16 _Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b) { return a * b; } -_Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b) +NOMIPS16 _Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b) { return a * b; } -_Fract test17 (_Fract a, _Fract b) +NOMIPS16 _Fract test17 (_Fract a, _Fract b) { return a * b; } -long _Fract test18 (long _Fract a, long _Fract b) +NOMIPS16 long _Fract test18 (long _Fract a, long _Fract b) { return a * b; } diff --git a/gcc/testsuite/gcc.target/mips/fixed-vector-type.c b/gcc/testsuite/gcc.target/mips/fixed-vector-type.c index 30dba5b6460e..08208f2c2d7f 100644 --- a/gcc/testsuite/gcc.target/mips/fixed-vector-type.c +++ b/gcc/testsuite/gcc.target/mips/fixed-vector-type.c @@ -21,112 +21,112 @@ typedef unsigned short _Accum v2uha __attribute__ ((vector_size(4))); typedef _Fract v2hq __attribute__ ((vector_size(4))); typedef short _Accum v2ha __attribute__ ((vector_size(4))); -sat_v2hq test1 (sat_v2hq a, sat_v2hq b) +NOMIPS16 sat_v2hq test1 (sat_v2hq a, sat_v2hq b) { return a + b; } -sat_v2ha test2 (sat_v2ha a, sat_v2ha b) +NOMIPS16 sat_v2ha test2 (sat_v2ha a, sat_v2ha b) { return a + b; } -sat_v2hq test3 (sat_v2hq a, sat_v2hq b) +NOMIPS16 sat_v2hq test3 (sat_v2hq a, sat_v2hq b) { return a - b; } -sat_v2ha test4 (sat_v2ha a, sat_v2ha b) +NOMIPS16 sat_v2ha test4 (sat_v2ha a, sat_v2ha b) { return a - b; } -sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b) +NOMIPS16 sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b) { return a + b; } -sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b) +NOMIPS16 sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b) { return a + b; } -sat_v2uha test7 (sat_v2uha a, sat_v2uha b) +NOMIPS16 sat_v2uha test7 (sat_v2uha a, sat_v2uha b) { return a + b; } -sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b) +NOMIPS16 sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b) { return a - b; } -sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b) +NOMIPS16 sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b) { return a - b; } -sat_v2uha test10 (sat_v2uha a, sat_v2uha b) +NOMIPS16 sat_v2uha test10 (sat_v2uha a, sat_v2uha b) { return a - b; } -sat_v2hq test11 (sat_v2hq a, sat_v2hq b) +NOMIPS16 sat_v2hq test11 (sat_v2hq a, sat_v2hq b) { return a * b; } -v2hq test12 (v2hq a, v2hq b) +NOMIPS16 v2hq test12 (v2hq a, v2hq b) { return a + b; } -v2hq test13 (v2hq a, v2hq b) +NOMIPS16 v2hq test13 (v2hq a, v2hq b) { return a - b; } -v2hq test14 (v2hq a, v2hq b) +NOMIPS16 v2hq test14 (v2hq a, v2hq b) { return a * b; } -v2ha test15 (v2ha a, v2ha b) +NOMIPS16 v2ha test15 (v2ha a, v2ha b) { return a + b; } -v2ha test16 (v2ha a, v2ha b) +NOMIPS16 v2ha test16 (v2ha a, v2ha b) { return a - b; } -v4uqq test17 (v4uqq a, v4uqq b) +NOMIPS16 v4uqq test17 (v4uqq a, v4uqq b) { return a + b; } -v4uqq test18 (v4uqq a, v4uqq b) +NOMIPS16 v4uqq test18 (v4uqq a, v4uqq b) { return a - b; } -v2uhq test19 (v2uhq a, v2uhq b) +NOMIPS16 v2uhq test19 (v2uhq a, v2uhq b) { return a + b; } -v2uhq test20 (v2uhq a, v2uhq b) +NOMIPS16 v2uhq test20 (v2uhq a, v2uhq b) { return a - b; } -v2uha test21 (v2uha a, v2uha b) +NOMIPS16 v2uha test21 (v2uha a, v2uha b) { return a + b; } -v2uha test22 (v2uha a, v2uha b) +NOMIPS16 v2uha test22 (v2uha a, v2uha b) { return a - b; } diff --git a/gcc/testsuite/gcc.target/mips/madd-1.c b/gcc/testsuite/gcc.target/mips/madd-1.c index e5223396e8d5..c0cdf4958968 100644 --- a/gcc/testsuite/gcc.target/mips/madd-1.c +++ b/gcc/testsuite/gcc.target/mips/madd-1.c @@ -2,19 +2,19 @@ /* { dg-mips-options "-O2 -march=vr4130 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return (long long) x * y + z; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { return z + (long long) y * x; } -long long +NOMIPS16 long long f3 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/madd-2.c b/gcc/testsuite/gcc.target/mips/madd-2.c index 4c761ed6ca4e..daadd416c035 100644 --- a/gcc/testsuite/gcc.target/mips/madd-2.c +++ b/gcc/testsuite/gcc.target/mips/madd-2.c @@ -2,19 +2,19 @@ /* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return (long long) x * y + z; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { return z + (long long) y * x; } -long long +NOMIPS16 long long f3 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/madd-4.c b/gcc/testsuite/gcc.target/mips/madd-4.c index 28b5534b6f3b..8bdf99fbb248 100644 --- a/gcc/testsuite/gcc.target/mips/madd-4.c +++ b/gcc/testsuite/gcc.target/mips/madd-4.c @@ -2,19 +2,19 @@ /* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return (long long) x * y + z; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { return z + (long long) y * x; } -long long +NOMIPS16 long long f3 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/maddu-1.c b/gcc/testsuite/gcc.target/mips/maddu-1.c index 961e49bcb3c9..254f3e75d542 100644 --- a/gcc/testsuite/gcc.target/mips/maddu-1.c +++ b/gcc/testsuite/gcc.target/mips/maddu-1.c @@ -5,19 +5,19 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return (ull) x * y + z; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { return z + (ull) y * x; } -ull +NOMIPS16 ull f3 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/maddu-2.c b/gcc/testsuite/gcc.target/mips/maddu-2.c index 2add97410ef5..fc1574e96676 100644 --- a/gcc/testsuite/gcc.target/mips/maddu-2.c +++ b/gcc/testsuite/gcc.target/mips/maddu-2.c @@ -5,19 +5,19 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return (ull) x * y + z; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { return z + (ull) y * x; } -ull +NOMIPS16 ull f3 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/maddu-4.c b/gcc/testsuite/gcc.target/mips/maddu-4.c index f208713ef8a2..2bc54f864712 100644 --- a/gcc/testsuite/gcc.target/mips/maddu-4.c +++ b/gcc/testsuite/gcc.target/mips/maddu-4.c @@ -5,19 +5,19 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return (ull) x * y + z; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { return z + (ull) y * x; } -ull +NOMIPS16 ull f3 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-1.c b/gcc/testsuite/gcc.target/mips/mips-3d-1.c index 765bc4910849..393ebfc71e9d 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-1.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-1.c @@ -7,7 +7,7 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int main () +NOMIPS16 int main () { int little_endian; v2sf a, b, c, d; diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-2.c b/gcc/testsuite/gcc.target/mips/mips-3d-2.c index fc70fa2de073..3c8850bb1aa2 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-2.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-2.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int test0 (v2sf a, v2sf b); -int test1 (v2sf a, v2sf b); -int test2 (v2sf a, v2sf b); -int test3 (v2sf a, v2sf b); -int test4 (v2sf a, v2sf b); -int test5 (v2sf a, v2sf b); -int test6 (v2sf a, v2sf b); -int test7 (v2sf a, v2sf b); -int test8 (v2sf a, v2sf b); -int test9 (v2sf a, v2sf b); -int test10 (v2sf a, v2sf b); -int test11 (v2sf a, v2sf b); -int test12 (v2sf a, v2sf b); -int test13 (v2sf a, v2sf b); -int test14 (v2sf a, v2sf b); -int test15 (v2sf a, v2sf b); -int test16 (v2sf a, v2sf b); -int test17 (v2sf a, v2sf b); -int test18 (v2sf a, v2sf b); -int test19 (v2sf a, v2sf b); -int test20 (v2sf a, v2sf b); -int test21 (v2sf a, v2sf b); -int test22 (v2sf a, v2sf b); -int test23 (v2sf a, v2sf b); -int test24 (v2sf a, v2sf b); -int test25 (v2sf a, v2sf b); -int test26 (v2sf a, v2sf b); -int test27 (v2sf a, v2sf b); -int test28 (v2sf a, v2sf b); -int test29 (v2sf a, v2sf b); -int test30 (v2sf a, v2sf b); -int test31 (v2sf a, v2sf b); +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { v2sf a, b, c, d; int i, j; @@ -393,162 +393,162 @@ int main () exit (0); } -int test0 (v2sf a, v2sf b) +NOMIPS16 int test0 (v2sf a, v2sf b) { return __builtin_mips_any_c_f_ps (a, b); } -int test1 (v2sf a, v2sf b) +NOMIPS16 int test1 (v2sf a, v2sf b) { return __builtin_mips_all_c_f_ps (a, b); } -int test2 (v2sf a, v2sf b) +NOMIPS16 int test2 (v2sf a, v2sf b) { return __builtin_mips_any_c_un_ps (a, b); } -int test3 (v2sf a, v2sf b) +NOMIPS16 int test3 (v2sf a, v2sf b) { return __builtin_mips_all_c_un_ps (a, b); } -int test4 (v2sf a, v2sf b) +NOMIPS16 int test4 (v2sf a, v2sf b) { return __builtin_mips_any_c_eq_ps (a, b); } -int test5 (v2sf a, v2sf b) +NOMIPS16 int test5 (v2sf a, v2sf b) { return __builtin_mips_all_c_eq_ps (a, b); } -int test6 (v2sf a, v2sf b) +NOMIPS16 int test6 (v2sf a, v2sf b) { return __builtin_mips_any_c_ueq_ps (a, b); } -int test7 (v2sf a, v2sf b) +NOMIPS16 int test7 (v2sf a, v2sf b) { return __builtin_mips_all_c_ueq_ps (a, b); } -int test8 (v2sf a, v2sf b) +NOMIPS16 int test8 (v2sf a, v2sf b) { return __builtin_mips_any_c_olt_ps (a, b); } -int test9 (v2sf a, v2sf b) +NOMIPS16 int test9 (v2sf a, v2sf b) { return __builtin_mips_all_c_olt_ps (a, b); } -int test10 (v2sf a, v2sf b) +NOMIPS16 int test10 (v2sf a, v2sf b) { return __builtin_mips_any_c_ult_ps (a, b); } -int test11 (v2sf a, v2sf b) +NOMIPS16 int test11 (v2sf a, v2sf b) { return __builtin_mips_all_c_ult_ps (a, b); } -int test12 (v2sf a, v2sf b) +NOMIPS16 int test12 (v2sf a, v2sf b) { return __builtin_mips_any_c_ole_ps (a, b); } -int test13 (v2sf a, v2sf b) +NOMIPS16 int test13 (v2sf a, v2sf b) { return __builtin_mips_all_c_ole_ps (a, b); } -int test14 (v2sf a, v2sf b) +NOMIPS16 int test14 (v2sf a, v2sf b) { return __builtin_mips_any_c_ule_ps (a, b); } -int test15 (v2sf a, v2sf b) +NOMIPS16 int test15 (v2sf a, v2sf b) { return __builtin_mips_all_c_ule_ps (a, b); } -int test16 (v2sf a, v2sf b) +NOMIPS16 int test16 (v2sf a, v2sf b) { return __builtin_mips_any_c_sf_ps (a, b); } -int test17 (v2sf a, v2sf b) +NOMIPS16 int test17 (v2sf a, v2sf b) { return __builtin_mips_all_c_sf_ps (a, b); } -int test18 (v2sf a, v2sf b) +NOMIPS16 int test18 (v2sf a, v2sf b) { return __builtin_mips_any_c_ngle_ps (a, b); } -int test19 (v2sf a, v2sf b) +NOMIPS16 int test19 (v2sf a, v2sf b) { return __builtin_mips_all_c_ngle_ps (a, b); } -int test20 (v2sf a, v2sf b) +NOMIPS16 int test20 (v2sf a, v2sf b) { return __builtin_mips_any_c_seq_ps (a, b); } -int test21 (v2sf a, v2sf b) +NOMIPS16 int test21 (v2sf a, v2sf b) { return __builtin_mips_all_c_seq_ps (a, b); } -int test22 (v2sf a, v2sf b) +NOMIPS16 int test22 (v2sf a, v2sf b) { return __builtin_mips_any_c_ngl_ps (a, b); } -int test23 (v2sf a, v2sf b) +NOMIPS16 int test23 (v2sf a, v2sf b) { return __builtin_mips_all_c_ngl_ps (a, b); } -int test24 (v2sf a, v2sf b) +NOMIPS16 int test24 (v2sf a, v2sf b) { return __builtin_mips_any_c_lt_ps (a, b); } -int test25 (v2sf a, v2sf b) +NOMIPS16 int test25 (v2sf a, v2sf b) { return __builtin_mips_all_c_lt_ps (a, b); } -int test26 (v2sf a, v2sf b) +NOMIPS16 int test26 (v2sf a, v2sf b) { return __builtin_mips_any_c_nge_ps (a, b); } -int test27 (v2sf a, v2sf b) +NOMIPS16 int test27 (v2sf a, v2sf b) { return __builtin_mips_all_c_nge_ps (a, b); } -int test28 (v2sf a, v2sf b) +NOMIPS16 int test28 (v2sf a, v2sf b) { return __builtin_mips_any_c_le_ps (a, b); } -int test29 (v2sf a, v2sf b) +NOMIPS16 int test29 (v2sf a, v2sf b) { return __builtin_mips_all_c_le_ps (a, b); } -int test30 (v2sf a, v2sf b) +NOMIPS16 int test30 (v2sf a, v2sf b) { return __builtin_mips_any_c_ngt_ps (a, b); } -int test31 (v2sf a, v2sf b) +NOMIPS16 int test31 (v2sf a, v2sf b) { return __builtin_mips_all_c_ngt_ps (a, b); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-3.c b/gcc/testsuite/gcc.target/mips/mips-3d-3.c index 81d6c25f93c2..909a89a24407 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-3.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-3.c @@ -7,74 +7,74 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int test0 (v2sf a, v2sf b); -int test1 (v2sf a, v2sf b); -int test2 (v2sf a, v2sf b); -int test3 (v2sf a, v2sf b); -int test4 (v2sf a, v2sf b); -int test5 (v2sf a, v2sf b); -int test6 (v2sf a, v2sf b); -int test7 (v2sf a, v2sf b); -int test8 (v2sf a, v2sf b); -int test9 (v2sf a, v2sf b); -int test10 (v2sf a, v2sf b); -int test11 (v2sf a, v2sf b); -int test12 (v2sf a, v2sf b); -int test13 (v2sf a, v2sf b); -int test14 (v2sf a, v2sf b); -int test15 (v2sf a, v2sf b); -int test16 (v2sf a, v2sf b); -int test17 (v2sf a, v2sf b); -int test18 (v2sf a, v2sf b); -int test19 (v2sf a, v2sf b); -int test20 (v2sf a, v2sf b); -int test21 (v2sf a, v2sf b); -int test22 (v2sf a, v2sf b); -int test23 (v2sf a, v2sf b); -int test24 (v2sf a, v2sf b); -int test25 (v2sf a, v2sf b); -int test26 (v2sf a, v2sf b); -int test27 (v2sf a, v2sf b); -int test28 (v2sf a, v2sf b); -int test29 (v2sf a, v2sf b); -int test30 (v2sf a, v2sf b); -int test31 (v2sf a, v2sf b); -int test32 (v2sf a, v2sf b); -int test33 (v2sf a, v2sf b); -int test34 (v2sf a, v2sf b); -int test35 (v2sf a, v2sf b); -int test36 (v2sf a, v2sf b); -int test37 (v2sf a, v2sf b); -int test38 (v2sf a, v2sf b); -int test39 (v2sf a, v2sf b); -int test40 (v2sf a, v2sf b); -int test41 (v2sf a, v2sf b); -int test42 (v2sf a, v2sf b); -int test43 (v2sf a, v2sf b); -int test44 (v2sf a, v2sf b); -int test45 (v2sf a, v2sf b); -int test46 (v2sf a, v2sf b); -int test47 (v2sf a, v2sf b); -int test48 (v2sf a, v2sf b); -int test49 (v2sf a, v2sf b); -int test50 (v2sf a, v2sf b); -int test51 (v2sf a, v2sf b); -int test52 (v2sf a, v2sf b); -int test53 (v2sf a, v2sf b); -int test54 (v2sf a, v2sf b); -int test55 (v2sf a, v2sf b); -int test56 (v2sf a, v2sf b); -int test57 (v2sf a, v2sf b); -int test58 (v2sf a, v2sf b); -int test59 (v2sf a, v2sf b); -int test60 (v2sf a, v2sf b); -int test61 (v2sf a, v2sf b); -int test62 (v2sf a, v2sf b); -int test63 (v2sf a, v2sf b); +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); +NOMIPS16 int test32 (v2sf a, v2sf b); +NOMIPS16 int test33 (v2sf a, v2sf b); +NOMIPS16 int test34 (v2sf a, v2sf b); +NOMIPS16 int test35 (v2sf a, v2sf b); +NOMIPS16 int test36 (v2sf a, v2sf b); +NOMIPS16 int test37 (v2sf a, v2sf b); +NOMIPS16 int test38 (v2sf a, v2sf b); +NOMIPS16 int test39 (v2sf a, v2sf b); +NOMIPS16 int test40 (v2sf a, v2sf b); +NOMIPS16 int test41 (v2sf a, v2sf b); +NOMIPS16 int test42 (v2sf a, v2sf b); +NOMIPS16 int test43 (v2sf a, v2sf b); +NOMIPS16 int test44 (v2sf a, v2sf b); +NOMIPS16 int test45 (v2sf a, v2sf b); +NOMIPS16 int test46 (v2sf a, v2sf b); +NOMIPS16 int test47 (v2sf a, v2sf b); +NOMIPS16 int test48 (v2sf a, v2sf b); +NOMIPS16 int test49 (v2sf a, v2sf b); +NOMIPS16 int test50 (v2sf a, v2sf b); +NOMIPS16 int test51 (v2sf a, v2sf b); +NOMIPS16 int test52 (v2sf a, v2sf b); +NOMIPS16 int test53 (v2sf a, v2sf b); +NOMIPS16 int test54 (v2sf a, v2sf b); +NOMIPS16 int test55 (v2sf a, v2sf b); +NOMIPS16 int test56 (v2sf a, v2sf b); +NOMIPS16 int test57 (v2sf a, v2sf b); +NOMIPS16 int test58 (v2sf a, v2sf b); +NOMIPS16 int test59 (v2sf a, v2sf b); +NOMIPS16 int test60 (v2sf a, v2sf b); +NOMIPS16 int test61 (v2sf a, v2sf b); +NOMIPS16 int test62 (v2sf a, v2sf b); +NOMIPS16 int test63 (v2sf a, v2sf b); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { int little_endian; v2sf a, b, c, d; @@ -774,322 +774,322 @@ int main () exit (0); } -int test0 (v2sf a, v2sf b) +NOMIPS16 int test0 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_f_ps (a, b); } -int test1 (v2sf a, v2sf b) +NOMIPS16 int test1 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_f_ps (a, b); } -int test2 (v2sf a, v2sf b) +NOMIPS16 int test2 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_f_ps (a, b); } -int test3 (v2sf a, v2sf b) +NOMIPS16 int test3 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_f_ps (a, b); } -int test4 (v2sf a, v2sf b) +NOMIPS16 int test4 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_un_ps (a, b); } -int test5 (v2sf a, v2sf b) +NOMIPS16 int test5 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_un_ps (a, b); } -int test6 (v2sf a, v2sf b) +NOMIPS16 int test6 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_un_ps (a, b); } -int test7 (v2sf a, v2sf b) +NOMIPS16 int test7 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_un_ps (a, b); } -int test8 (v2sf a, v2sf b) +NOMIPS16 int test8 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_eq_ps (a, b); } -int test9 (v2sf a, v2sf b) +NOMIPS16 int test9 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_eq_ps (a, b); } -int test10 (v2sf a, v2sf b) +NOMIPS16 int test10 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_eq_ps (a, b); } -int test11 (v2sf a, v2sf b) +NOMIPS16 int test11 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_eq_ps (a, b); } -int test12 (v2sf a, v2sf b) +NOMIPS16 int test12 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ueq_ps (a, b); } -int test13 (v2sf a, v2sf b) +NOMIPS16 int test13 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ueq_ps (a, b); } -int test14 (v2sf a, v2sf b) +NOMIPS16 int test14 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ueq_ps (a, b); } -int test15 (v2sf a, v2sf b) +NOMIPS16 int test15 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ueq_ps (a, b); } -int test16 (v2sf a, v2sf b) +NOMIPS16 int test16 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_olt_ps (a, b); } -int test17 (v2sf a, v2sf b) +NOMIPS16 int test17 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_olt_ps (a, b); } -int test18 (v2sf a, v2sf b) +NOMIPS16 int test18 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_olt_ps (a, b); } -int test19 (v2sf a, v2sf b) +NOMIPS16 int test19 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_olt_ps (a, b); } -int test20 (v2sf a, v2sf b) +NOMIPS16 int test20 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ult_ps (a, b); } -int test21 (v2sf a, v2sf b) +NOMIPS16 int test21 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ult_ps (a, b); } -int test22 (v2sf a, v2sf b) +NOMIPS16 int test22 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ult_ps (a, b); } -int test23 (v2sf a, v2sf b) +NOMIPS16 int test23 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ult_ps (a, b); } -int test24 (v2sf a, v2sf b) +NOMIPS16 int test24 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ole_ps (a, b); } -int test25 (v2sf a, v2sf b) +NOMIPS16 int test25 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ole_ps (a, b); } -int test26 (v2sf a, v2sf b) +NOMIPS16 int test26 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ole_ps (a, b); } -int test27 (v2sf a, v2sf b) +NOMIPS16 int test27 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ole_ps (a, b); } -int test28 (v2sf a, v2sf b) +NOMIPS16 int test28 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ule_ps (a, b); } -int test29 (v2sf a, v2sf b) +NOMIPS16 int test29 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ule_ps (a, b); } -int test30 (v2sf a, v2sf b) +NOMIPS16 int test30 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ule_ps (a, b); } -int test31 (v2sf a, v2sf b) +NOMIPS16 int test31 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ule_ps (a, b); } -int test32 (v2sf a, v2sf b) +NOMIPS16 int test32 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_sf_ps (a, b); } -int test33 (v2sf a, v2sf b) +NOMIPS16 int test33 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_sf_ps (a, b); } -int test34 (v2sf a, v2sf b) +NOMIPS16 int test34 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_sf_ps (a, b); } -int test35 (v2sf a, v2sf b) +NOMIPS16 int test35 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_sf_ps (a, b); } -int test36 (v2sf a, v2sf b) +NOMIPS16 int test36 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ngle_ps (a, b); } -int test37 (v2sf a, v2sf b) +NOMIPS16 int test37 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ngle_ps (a, b); } -int test38 (v2sf a, v2sf b) +NOMIPS16 int test38 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ngle_ps (a, b); } -int test39 (v2sf a, v2sf b) +NOMIPS16 int test39 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ngle_ps (a, b); } -int test40 (v2sf a, v2sf b) +NOMIPS16 int test40 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_seq_ps (a, b); } -int test41 (v2sf a, v2sf b) +NOMIPS16 int test41 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_seq_ps (a, b); } -int test42 (v2sf a, v2sf b) +NOMIPS16 int test42 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_seq_ps (a, b); } -int test43 (v2sf a, v2sf b) +NOMIPS16 int test43 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_seq_ps (a, b); } -int test44 (v2sf a, v2sf b) +NOMIPS16 int test44 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ngl_ps (a, b); } -int test45 (v2sf a, v2sf b) +NOMIPS16 int test45 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ngl_ps (a, b); } -int test46 (v2sf a, v2sf b) +NOMIPS16 int test46 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ngl_ps (a, b); } -int test47 (v2sf a, v2sf b) +NOMIPS16 int test47 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ngl_ps (a, b); } -int test48 (v2sf a, v2sf b) +NOMIPS16 int test48 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_lt_ps (a, b); } -int test49 (v2sf a, v2sf b) +NOMIPS16 int test49 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_lt_ps (a, b); } -int test50 (v2sf a, v2sf b) +NOMIPS16 int test50 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_lt_ps (a, b); } -int test51 (v2sf a, v2sf b) +NOMIPS16 int test51 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_lt_ps (a, b); } -int test52 (v2sf a, v2sf b) +NOMIPS16 int test52 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_nge_ps (a, b); } -int test53 (v2sf a, v2sf b) +NOMIPS16 int test53 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_nge_ps (a, b); } -int test54 (v2sf a, v2sf b) +NOMIPS16 int test54 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_nge_ps (a, b); } -int test55 (v2sf a, v2sf b) +NOMIPS16 int test55 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_nge_ps (a, b); } -int test56 (v2sf a, v2sf b) +NOMIPS16 int test56 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_le_ps (a, b); } -int test57 (v2sf a, v2sf b) +NOMIPS16 int test57 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_le_ps (a, b); } -int test58 (v2sf a, v2sf b) +NOMIPS16 int test58 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_le_ps (a, b); } -int test59 (v2sf a, v2sf b) +NOMIPS16 int test59 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_le_ps (a, b); } -int test60 (v2sf a, v2sf b) +NOMIPS16 int test60 (v2sf a, v2sf b) { return __builtin_mips_any_cabs_ngt_ps (a, b); } -int test61 (v2sf a, v2sf b) +NOMIPS16 int test61 (v2sf a, v2sf b) { return __builtin_mips_upper_cabs_ngt_ps (a, b); } -int test62 (v2sf a, v2sf b) +NOMIPS16 int test62 (v2sf a, v2sf b) { return __builtin_mips_lower_cabs_ngt_ps (a, b); } -int test63 (v2sf a, v2sf b) +NOMIPS16 int test63 (v2sf a, v2sf b) { return __builtin_mips_all_cabs_ngt_ps (a, b); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-4.c b/gcc/testsuite/gcc.target/mips/mips-3d-4.c index b2b6bfe14d52..058ff2c3c8ee 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-4.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-4.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int test0 (v2sf a, v2sf b, v2sf c, v2sf d); -int test1 (v2sf a, v2sf b, v2sf c, v2sf d); -int test2 (v2sf a, v2sf b, v2sf c, v2sf d); -int test3 (v2sf a, v2sf b, v2sf c, v2sf d); -int test4 (v2sf a, v2sf b, v2sf c, v2sf d); -int test5 (v2sf a, v2sf b, v2sf c, v2sf d); -int test6 (v2sf a, v2sf b, v2sf c, v2sf d); -int test7 (v2sf a, v2sf b, v2sf c, v2sf d); -int test8 (v2sf a, v2sf b, v2sf c, v2sf d); -int test9 (v2sf a, v2sf b, v2sf c, v2sf d); -int test10 (v2sf a, v2sf b, v2sf c, v2sf d); -int test11 (v2sf a, v2sf b, v2sf c, v2sf d); -int test12 (v2sf a, v2sf b, v2sf c, v2sf d); -int test13 (v2sf a, v2sf b, v2sf c, v2sf d); -int test14 (v2sf a, v2sf b, v2sf c, v2sf d); -int test15 (v2sf a, v2sf b, v2sf c, v2sf d); -int test16 (v2sf a, v2sf b, v2sf c, v2sf d); -int test17 (v2sf a, v2sf b, v2sf c, v2sf d); -int test18 (v2sf a, v2sf b, v2sf c, v2sf d); -int test19 (v2sf a, v2sf b, v2sf c, v2sf d); -int test20 (v2sf a, v2sf b, v2sf c, v2sf d); -int test21 (v2sf a, v2sf b, v2sf c, v2sf d); -int test22 (v2sf a, v2sf b, v2sf c, v2sf d); -int test23 (v2sf a, v2sf b, v2sf c, v2sf d); -int test24 (v2sf a, v2sf b, v2sf c, v2sf d); -int test25 (v2sf a, v2sf b, v2sf c, v2sf d); -int test26 (v2sf a, v2sf b, v2sf c, v2sf d); -int test27 (v2sf a, v2sf b, v2sf c, v2sf d); -int test28 (v2sf a, v2sf b, v2sf c, v2sf d); -int test29 (v2sf a, v2sf b, v2sf c, v2sf d); -int test30 (v2sf a, v2sf b, v2sf c, v2sf d); -int test31 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { v2sf a, b, c, d; int i, j; @@ -429,162 +429,162 @@ int main () exit (0); } -int test0 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_f_4s (a, b, c, d); } -int test1 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_f_4s (a, b, c, d); } -int test2 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_un_4s (a, b, c, d); } -int test3 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_un_4s (a, b, c, d); } -int test4 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_eq_4s (a, b, c, d); } -int test5 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_eq_4s (a, b, c, d); } -int test6 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ueq_4s (a, b, c, d); } -int test7 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ueq_4s (a, b, c, d); } -int test8 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_olt_4s (a, b, c, d); } -int test9 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_olt_4s (a, b, c, d); } -int test10 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ult_4s (a, b, c, d); } -int test11 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ult_4s (a, b, c, d); } -int test12 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ole_4s (a, b, c, d); } -int test13 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ole_4s (a, b, c, d); } -int test14 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ule_4s (a, b, c, d); } -int test15 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ule_4s (a, b, c, d); } -int test16 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_sf_4s (a, b, c, d); } -int test17 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_sf_4s (a, b, c, d); } -int test18 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ngle_4s (a, b, c, d); } -int test19 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ngle_4s (a, b, c, d); } -int test20 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_seq_4s (a, b, c, d); } -int test21 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_seq_4s (a, b, c, d); } -int test22 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ngl_4s (a, b, c, d); } -int test23 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ngl_4s (a, b, c, d); } -int test24 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_lt_4s (a, b, c, d); } -int test25 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_lt_4s (a, b, c, d); } -int test26 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_nge_4s (a, b, c, d); } -int test27 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_nge_4s (a, b, c, d); } -int test28 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_le_4s (a, b, c, d); } -int test29 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_le_4s (a, b, c, d); } -int test30 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_c_ngt_4s (a, b, c, d); } -int test31 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_c_ngt_4s (a, b, c, d); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-5.c b/gcc/testsuite/gcc.target/mips/mips-3d-5.c index 7dc6d28e0eae..a98e579e7319 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-5.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-5.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int test0 (v2sf a, v2sf b, v2sf c, v2sf d); -int test1 (v2sf a, v2sf b, v2sf c, v2sf d); -int test2 (v2sf a, v2sf b, v2sf c, v2sf d); -int test3 (v2sf a, v2sf b, v2sf c, v2sf d); -int test4 (v2sf a, v2sf b, v2sf c, v2sf d); -int test5 (v2sf a, v2sf b, v2sf c, v2sf d); -int test6 (v2sf a, v2sf b, v2sf c, v2sf d); -int test7 (v2sf a, v2sf b, v2sf c, v2sf d); -int test8 (v2sf a, v2sf b, v2sf c, v2sf d); -int test9 (v2sf a, v2sf b, v2sf c, v2sf d); -int test10 (v2sf a, v2sf b, v2sf c, v2sf d); -int test11 (v2sf a, v2sf b, v2sf c, v2sf d); -int test12 (v2sf a, v2sf b, v2sf c, v2sf d); -int test13 (v2sf a, v2sf b, v2sf c, v2sf d); -int test14 (v2sf a, v2sf b, v2sf c, v2sf d); -int test15 (v2sf a, v2sf b, v2sf c, v2sf d); -int test16 (v2sf a, v2sf b, v2sf c, v2sf d); -int test17 (v2sf a, v2sf b, v2sf c, v2sf d); -int test18 (v2sf a, v2sf b, v2sf c, v2sf d); -int test19 (v2sf a, v2sf b, v2sf c, v2sf d); -int test20 (v2sf a, v2sf b, v2sf c, v2sf d); -int test21 (v2sf a, v2sf b, v2sf c, v2sf d); -int test22 (v2sf a, v2sf b, v2sf c, v2sf d); -int test23 (v2sf a, v2sf b, v2sf c, v2sf d); -int test24 (v2sf a, v2sf b, v2sf c, v2sf d); -int test25 (v2sf a, v2sf b, v2sf c, v2sf d); -int test26 (v2sf a, v2sf b, v2sf c, v2sf d); -int test27 (v2sf a, v2sf b, v2sf c, v2sf d); -int test28 (v2sf a, v2sf b, v2sf c, v2sf d); -int test29 (v2sf a, v2sf b, v2sf c, v2sf d); -int test30 (v2sf a, v2sf b, v2sf c, v2sf d); -int test31 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { v2sf a, b, c, d; int i, j; @@ -429,162 +429,162 @@ int main () exit (0); } -int test0 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_f_4s (a, b, c, d); } -int test1 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_f_4s (a, b, c, d); } -int test2 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_un_4s (a, b, c, d); } -int test3 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_un_4s (a, b, c, d); } -int test4 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_eq_4s (a, b, c, d); } -int test5 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_eq_4s (a, b, c, d); } -int test6 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ueq_4s (a, b, c, d); } -int test7 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ueq_4s (a, b, c, d); } -int test8 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_olt_4s (a, b, c, d); } -int test9 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_olt_4s (a, b, c, d); } -int test10 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ult_4s (a, b, c, d); } -int test11 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ult_4s (a, b, c, d); } -int test12 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ole_4s (a, b, c, d); } -int test13 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ole_4s (a, b, c, d); } -int test14 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ule_4s (a, b, c, d); } -int test15 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ule_4s (a, b, c, d); } -int test16 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_sf_4s (a, b, c, d); } -int test17 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_sf_4s (a, b, c, d); } -int test18 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ngle_4s (a, b, c, d); } -int test19 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ngle_4s (a, b, c, d); } -int test20 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_seq_4s (a, b, c, d); } -int test21 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_seq_4s (a, b, c, d); } -int test22 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ngl_4s (a, b, c, d); } -int test23 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ngl_4s (a, b, c, d); } -int test24 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_lt_4s (a, b, c, d); } -int test25 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_lt_4s (a, b, c, d); } -int test26 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_nge_4s (a, b, c, d); } -int test27 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_nge_4s (a, b, c, d); } -int test28 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_le_4s (a, b, c, d); } -int test29 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_le_4s (a, b, c, d); } -int test30 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_any_cabs_ngt_4s (a, b, c, d); } -int test31 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_all_cabs_ngt_4s (a, b, c, d); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-6.c b/gcc/testsuite/gcc.target/mips/mips-3d-6.c index 5a7622dd0e89..30715ea31a37 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-6.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-6.c @@ -5,24 +5,24 @@ #include #include -int test0 (float a, float b); -int test1 (float a, float b); -int test2 (float a, float b); -int test3 (float a, float b); -int test4 (float a, float b); -int test5 (float a, float b); -int test6 (float a, float b); -int test7 (float a, float b); -int test8 (float a, float b); -int test9 (float a, float b); -int test10 (float a, float b); -int test11 (float a, float b); -int test12 (float a, float b); -int test13 (float a, float b); -int test14 (float a, float b); -int test15 (float a, float b); +NOMIPS16 int test0 (float a, float b); +NOMIPS16 int test1 (float a, float b); +NOMIPS16 int test2 (float a, float b); +NOMIPS16 int test3 (float a, float b); +NOMIPS16 int test4 (float a, float b); +NOMIPS16 int test5 (float a, float b); +NOMIPS16 int test6 (float a, float b); +NOMIPS16 int test7 (float a, float b); +NOMIPS16 int test8 (float a, float b); +NOMIPS16 int test9 (float a, float b); +NOMIPS16 int test10 (float a, float b); +NOMIPS16 int test11 (float a, float b); +NOMIPS16 int test12 (float a, float b); +NOMIPS16 int test13 (float a, float b); +NOMIPS16 int test14 (float a, float b); +NOMIPS16 int test15 (float a, float b); -int main () +NOMIPS16 int main () { float a, b; int i; @@ -203,82 +203,82 @@ int main () exit (0); } -int test0 (float a, float b) +NOMIPS16 int test0 (float a, float b) { return __builtin_mips_cabs_f_s (a, b); } -int test1 (float a, float b) +NOMIPS16 int test1 (float a, float b) { return __builtin_mips_cabs_un_s (a, b); } -int test2 (float a, float b) +NOMIPS16 int test2 (float a, float b) { return __builtin_mips_cabs_eq_s (a, b); } -int test3 (float a, float b) +NOMIPS16 int test3 (float a, float b) { return __builtin_mips_cabs_ueq_s (a, b); } -int test4 (float a, float b) +NOMIPS16 int test4 (float a, float b) { return __builtin_mips_cabs_olt_s (a, b); } -int test5 (float a, float b) +NOMIPS16 int test5 (float a, float b) { return __builtin_mips_cabs_ult_s (a, b); } -int test6 (float a, float b) +NOMIPS16 int test6 (float a, float b) { return __builtin_mips_cabs_ole_s (a, b); } -int test7 (float a, float b) +NOMIPS16 int test7 (float a, float b) { return __builtin_mips_cabs_ule_s (a, b); } -int test8 (float a, float b) +NOMIPS16 int test8 (float a, float b) { return __builtin_mips_cabs_sf_s (a, b); } -int test9 (float a, float b) +NOMIPS16 int test9 (float a, float b) { return __builtin_mips_cabs_ngle_s (a, b); } -int test10 (float a, float b) +NOMIPS16 int test10 (float a, float b) { return __builtin_mips_cabs_seq_s (a, b); } -int test11 (float a, float b) +NOMIPS16 int test11 (float a, float b) { return __builtin_mips_cabs_ngl_s (a, b); } -int test12 (float a, float b) +NOMIPS16 int test12 (float a, float b) { return __builtin_mips_cabs_lt_s (a, b); } -int test13 (float a, float b) +NOMIPS16 int test13 (float a, float b) { return __builtin_mips_cabs_nge_s (a, b); } -int test14 (float a, float b) +NOMIPS16 int test14 (float a, float b) { return __builtin_mips_cabs_le_s (a, b); } -int test15 (float a, float b) +NOMIPS16 int test15 (float a, float b) { return __builtin_mips_cabs_ngt_s (a, b); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-7.c b/gcc/testsuite/gcc.target/mips/mips-3d-7.c index 3a512f4a1136..0eef933b2ee2 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-7.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-7.c @@ -5,24 +5,24 @@ #include #include -int test0 (double a, double b); -int test1 (double a, double b); -int test2 (double a, double b); -int test3 (double a, double b); -int test4 (double a, double b); -int test5 (double a, double b); -int test6 (double a, double b); -int test7 (double a, double b); -int test8 (double a, double b); -int test9 (double a, double b); -int test10 (double a, double b); -int test11 (double a, double b); -int test12 (double a, double b); -int test13 (double a, double b); -int test14 (double a, double b); -int test15 (double a, double b); +NOMIPS16 int test0 (double a, double b); +NOMIPS16 int test1 (double a, double b); +NOMIPS16 int test2 (double a, double b); +NOMIPS16 int test3 (double a, double b); +NOMIPS16 int test4 (double a, double b); +NOMIPS16 int test5 (double a, double b); +NOMIPS16 int test6 (double a, double b); +NOMIPS16 int test7 (double a, double b); +NOMIPS16 int test8 (double a, double b); +NOMIPS16 int test9 (double a, double b); +NOMIPS16 int test10 (double a, double b); +NOMIPS16 int test11 (double a, double b); +NOMIPS16 int test12 (double a, double b); +NOMIPS16 int test13 (double a, double b); +NOMIPS16 int test14 (double a, double b); +NOMIPS16 int test15 (double a, double b); -int main () +NOMIPS16 int main () { double a, b; int i; @@ -203,82 +203,82 @@ int main () exit (0); } -int test0 (double a, double b) +NOMIPS16 int test0 (double a, double b) { return __builtin_mips_cabs_f_d (a, b); } -int test1 (double a, double b) +NOMIPS16 int test1 (double a, double b) { return __builtin_mips_cabs_un_d (a, b); } -int test2 (double a, double b) +NOMIPS16 int test2 (double a, double b) { return __builtin_mips_cabs_eq_d (a, b); } -int test3 (double a, double b) +NOMIPS16 int test3 (double a, double b) { return __builtin_mips_cabs_ueq_d (a, b); } -int test4 (double a, double b) +NOMIPS16 int test4 (double a, double b) { return __builtin_mips_cabs_olt_d (a, b); } -int test5 (double a, double b) +NOMIPS16 int test5 (double a, double b) { return __builtin_mips_cabs_ult_d (a, b); } -int test6 (double a, double b) +NOMIPS16 int test6 (double a, double b) { return __builtin_mips_cabs_ole_d (a, b); } -int test7 (double a, double b) +NOMIPS16 int test7 (double a, double b) { return __builtin_mips_cabs_ule_d (a, b); } -int test8 (double a, double b) +NOMIPS16 int test8 (double a, double b) { return __builtin_mips_cabs_sf_d (a, b); } -int test9 (double a, double b) +NOMIPS16 int test9 (double a, double b) { return __builtin_mips_cabs_ngle_d (a, b); } -int test10 (double a, double b) +NOMIPS16 int test10 (double a, double b) { return __builtin_mips_cabs_seq_d (a, b); } -int test11 (double a, double b) +NOMIPS16 int test11 (double a, double b) { return __builtin_mips_cabs_ngl_d (a, b); } -int test12 (double a, double b) +NOMIPS16 int test12 (double a, double b) { return __builtin_mips_cabs_lt_d (a, b); } -int test13 (double a, double b) +NOMIPS16 int test13 (double a, double b) { return __builtin_mips_cabs_nge_d (a, b); } -int test14 (double a, double b) +NOMIPS16 int test14 (double a, double b) { return __builtin_mips_cabs_le_d (a, b); } -int test15 (double a, double b) +NOMIPS16 int test15 (double a, double b) { return __builtin_mips_cabs_ngt_d (a, b); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-8.c b/gcc/testsuite/gcc.target/mips/mips-3d-8.c index 601e5ff30a48..042a73066b13 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-8.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-8.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__((vector_size(8))); -v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { v2sf a, b, c, d, e, f; @@ -469,162 +469,162 @@ int main () exit (0); } -v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_f_ps (a, b, c, d); } -v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_f_ps (a, b, c, d); } -v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_un_ps (a, b, c, d); } -v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_un_ps (a, b, c, d); } -v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_eq_ps (a, b, c, d); } -v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_eq_ps (a, b, c, d); } -v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ueq_ps (a, b, c, d); } -v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ueq_ps (a, b, c, d); } -v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_olt_ps (a, b, c, d); } -v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_olt_ps (a, b, c, d); } -v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ult_ps (a, b, c, d); } -v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ult_ps (a, b, c, d); } -v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ole_ps (a, b, c, d); } -v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ole_ps (a, b, c, d); } -v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ule_ps (a, b, c, d); } -v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ule_ps (a, b, c, d); } -v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_sf_ps (a, b, c, d); } -v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_sf_ps (a, b, c, d); } -v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ngle_ps (a, b, c, d); } -v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ngle_ps (a, b, c, d); } -v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_seq_ps (a, b, c, d); } -v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_seq_ps (a, b, c, d); } -v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ngl_ps (a, b, c, d); } -v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ngl_ps (a, b, c, d); } -v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_lt_ps (a, b, c, d); } -v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_lt_ps (a, b, c, d); } -v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_nge_ps (a, b, c, d); } -v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_nge_ps (a, b, c, d); } -v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_le_ps (a, b, c, d); } -v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_le_ps (a, b, c, d); } -v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_cabs_ngt_ps (a, b, c, d); } -v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_cabs_ngt_ps (a, b, c, d); } diff --git a/gcc/testsuite/gcc.target/mips/mips-3d-9.c b/gcc/testsuite/gcc.target/mips/mips-3d-9.c index 11d863f352d4..fdfedcbeae31 100644 --- a/gcc/testsuite/gcc.target/mips/mips-3d-9.c +++ b/gcc/testsuite/gcc.target/mips/mips-3d-9.c @@ -19,9 +19,9 @@ float e[4]; /* Result for matrix_multiply3() */ float f[4]; /* Result for matrix_multiply4() */ void matrix_multiply1(); -void matrix_multiply2(); -void matrix_multiply3(); -void matrix_multiply4(); +NOMIPS16 void matrix_multiply2(); +NOMIPS16 void matrix_multiply3(); +NOMIPS16 void matrix_multiply4(); int main () { @@ -65,7 +65,7 @@ void matrix_multiply1() } } -void matrix_multiply2() +NOMIPS16 void matrix_multiply2() { int i, j; v2sf m1, m2; @@ -91,7 +91,7 @@ void matrix_multiply2() } } -void matrix_multiply3() +NOMIPS16 void matrix_multiply3() { int i; v2sf m1, m2, n1, n2; @@ -114,7 +114,7 @@ void matrix_multiply3() } } -void matrix_multiply4() +NOMIPS16 void matrix_multiply4() { v2sf m1, m2; v2sf n1, n2, n3, n4, n5, n6, n7, n8; diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-1.c b/gcc/testsuite/gcc.target/mips/mips-ps-1.c index 1723933839f6..39fb996615a2 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-1.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-1.c @@ -117,7 +117,7 @@ v2sf cond_move4 (v2sf a, v2sf b, double i) return b; } -int main() +NOMIPS16 int main() { v2sf a, b, c, d, e, f; float f1, f2; diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-2.c b/gcc/testsuite/gcc.target/mips/mips-ps-2.c index 178bb910d8c4..69e8b2fc3eb0 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-2.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-2.c @@ -7,7 +7,7 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int main () +NOMIPS16 int main () { int little_endian; v2sf a, b, c, d; diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-3.c b/gcc/testsuite/gcc.target/mips/mips-ps-3.c index 8d29cc9b6be9..5894186dd261 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-3.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-3.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__((vector_size(8))); -v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); -v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d); +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main () +NOMIPS16 int main () { float f1; v2sf a, b, c, d, e, f; @@ -576,162 +576,162 @@ int main () exit (0); } -v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_f_ps (a, b, c, d); } -v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_f_ps (a, b, c, d); } -v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_un_ps (a, b, c, d); } -v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_un_ps (a, b, c, d); } -v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_eq_ps (a, b, c, d); } -v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_eq_ps (a, b, c, d); } -v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ueq_ps (a, b, c, d); } -v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ueq_ps (a, b, c, d); } -v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_olt_ps (a, b, c, d); } -v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_olt_ps (a, b, c, d); } -v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ult_ps (a, b, c, d); } -v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ult_ps (a, b, c, d); } -v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ole_ps (a, b, c, d); } -v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ole_ps (a, b, c, d); } -v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ule_ps (a, b, c, d); } -v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ule_ps (a, b, c, d); } -v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_sf_ps (a, b, c, d); } -v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_sf_ps (a, b, c, d); } -v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ngle_ps (a, b, c, d); } -v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ngle_ps (a, b, c, d); } -v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_seq_ps (a, b, c, d); } -v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_seq_ps (a, b, c, d); } -v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ngl_ps (a, b, c, d); } -v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ngl_ps (a, b, c, d); } -v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_lt_ps (a, b, c, d); } -v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_lt_ps (a, b, c, d); } -v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_nge_ps (a, b, c, d); } -v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_nge_ps (a, b, c, d); } -v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_le_ps (a, b, c, d); } -v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_le_ps (a, b, c, d); } -v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movt_c_ngt_ps (a, b, c, d); } -v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) +NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d) { return __builtin_mips_movf_c_ngt_ps (a, b, c, d); } diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-4.c b/gcc/testsuite/gcc.target/mips/mips-ps-4.c index 41c39dcaa228..1302db3941c1 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-4.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-4.c @@ -7,42 +7,42 @@ typedef float v2sf __attribute__((vector_size(8))); -int test0 (v2sf a, v2sf b); -int test1 (v2sf a, v2sf b); -int test2 (v2sf a, v2sf b); -int test3 (v2sf a, v2sf b); -int test4 (v2sf a, v2sf b); -int test5 (v2sf a, v2sf b); -int test6 (v2sf a, v2sf b); -int test7 (v2sf a, v2sf b); -int test8 (v2sf a, v2sf b); -int test9 (v2sf a, v2sf b); -int test10 (v2sf a, v2sf b); -int test11 (v2sf a, v2sf b); -int test12 (v2sf a, v2sf b); -int test13 (v2sf a, v2sf b); -int test14 (v2sf a, v2sf b); -int test15 (v2sf a, v2sf b); -int test16 (v2sf a, v2sf b); -int test17 (v2sf a, v2sf b); -int test18 (v2sf a, v2sf b); -int test19 (v2sf a, v2sf b); -int test20 (v2sf a, v2sf b); -int test21 (v2sf a, v2sf b); -int test22 (v2sf a, v2sf b); -int test23 (v2sf a, v2sf b); -int test24 (v2sf a, v2sf b); -int test25 (v2sf a, v2sf b); -int test26 (v2sf a, v2sf b); -int test27 (v2sf a, v2sf b); -int test28 (v2sf a, v2sf b); -int test29 (v2sf a, v2sf b); -int test30 (v2sf a, v2sf b); -int test31 (v2sf a, v2sf b); +NOMIPS16 int test0 (v2sf a, v2sf b); +NOMIPS16 int test1 (v2sf a, v2sf b); +NOMIPS16 int test2 (v2sf a, v2sf b); +NOMIPS16 int test3 (v2sf a, v2sf b); +NOMIPS16 int test4 (v2sf a, v2sf b); +NOMIPS16 int test5 (v2sf a, v2sf b); +NOMIPS16 int test6 (v2sf a, v2sf b); +NOMIPS16 int test7 (v2sf a, v2sf b); +NOMIPS16 int test8 (v2sf a, v2sf b); +NOMIPS16 int test9 (v2sf a, v2sf b); +NOMIPS16 int test10 (v2sf a, v2sf b); +NOMIPS16 int test11 (v2sf a, v2sf b); +NOMIPS16 int test12 (v2sf a, v2sf b); +NOMIPS16 int test13 (v2sf a, v2sf b); +NOMIPS16 int test14 (v2sf a, v2sf b); +NOMIPS16 int test15 (v2sf a, v2sf b); +NOMIPS16 int test16 (v2sf a, v2sf b); +NOMIPS16 int test17 (v2sf a, v2sf b); +NOMIPS16 int test18 (v2sf a, v2sf b); +NOMIPS16 int test19 (v2sf a, v2sf b); +NOMIPS16 int test20 (v2sf a, v2sf b); +NOMIPS16 int test21 (v2sf a, v2sf b); +NOMIPS16 int test22 (v2sf a, v2sf b); +NOMIPS16 int test23 (v2sf a, v2sf b); +NOMIPS16 int test24 (v2sf a, v2sf b); +NOMIPS16 int test25 (v2sf a, v2sf b); +NOMIPS16 int test26 (v2sf a, v2sf b); +NOMIPS16 int test27 (v2sf a, v2sf b); +NOMIPS16 int test28 (v2sf a, v2sf b); +NOMIPS16 int test29 (v2sf a, v2sf b); +NOMIPS16 int test30 (v2sf a, v2sf b); +NOMIPS16 int test31 (v2sf a, v2sf b); float qnan = 1.0f/0.0f - 1.0f/0.0f; -int main() +NOMIPS16 int main() { union { long long ll; int i[2]; } endianness_test; int little_endian; @@ -422,162 +422,162 @@ int main() exit (0); } -int test0 (v2sf a, v2sf b) +NOMIPS16 int test0 (v2sf a, v2sf b) { return __builtin_mips_upper_c_f_ps (a, b); } -int test1 (v2sf a, v2sf b) +NOMIPS16 int test1 (v2sf a, v2sf b) { return __builtin_mips_lower_c_f_ps (a, b); } -int test2 (v2sf a, v2sf b) +NOMIPS16 int test2 (v2sf a, v2sf b) { return __builtin_mips_upper_c_un_ps (a, b); } -int test3 (v2sf a, v2sf b) +NOMIPS16 int test3 (v2sf a, v2sf b) { return __builtin_mips_lower_c_un_ps (a, b); } -int test4 (v2sf a, v2sf b) +NOMIPS16 int test4 (v2sf a, v2sf b) { return __builtin_mips_upper_c_eq_ps (a, b); } -int test5 (v2sf a, v2sf b) +NOMIPS16 int test5 (v2sf a, v2sf b) { return __builtin_mips_lower_c_eq_ps (a, b); } -int test6 (v2sf a, v2sf b) +NOMIPS16 int test6 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ueq_ps (a, b); } -int test7 (v2sf a, v2sf b) +NOMIPS16 int test7 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ueq_ps (a, b); } -int test8 (v2sf a, v2sf b) +NOMIPS16 int test8 (v2sf a, v2sf b) { return __builtin_mips_upper_c_olt_ps (a, b); } -int test9 (v2sf a, v2sf b) +NOMIPS16 int test9 (v2sf a, v2sf b) { return __builtin_mips_lower_c_olt_ps (a, b); } -int test10 (v2sf a, v2sf b) +NOMIPS16 int test10 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ult_ps (a, b); } -int test11 (v2sf a, v2sf b) +NOMIPS16 int test11 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ult_ps (a, b); } -int test12 (v2sf a, v2sf b) +NOMIPS16 int test12 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ole_ps (a, b); } -int test13 (v2sf a, v2sf b) +NOMIPS16 int test13 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ole_ps (a, b); } -int test14 (v2sf a, v2sf b) +NOMIPS16 int test14 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ule_ps (a, b); } -int test15 (v2sf a, v2sf b) +NOMIPS16 int test15 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ule_ps (a, b); } -int test16 (v2sf a, v2sf b) +NOMIPS16 int test16 (v2sf a, v2sf b) { return __builtin_mips_upper_c_sf_ps (a, b); } -int test17 (v2sf a, v2sf b) +NOMIPS16 int test17 (v2sf a, v2sf b) { return __builtin_mips_lower_c_sf_ps (a, b); } -int test18 (v2sf a, v2sf b) +NOMIPS16 int test18 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ngle_ps (a, b); } -int test19 (v2sf a, v2sf b) +NOMIPS16 int test19 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ngle_ps (a, b); } -int test20 (v2sf a, v2sf b) +NOMIPS16 int test20 (v2sf a, v2sf b) { return __builtin_mips_upper_c_seq_ps (a, b); } -int test21 (v2sf a, v2sf b) +NOMIPS16 int test21 (v2sf a, v2sf b) { return __builtin_mips_lower_c_seq_ps (a, b); } -int test22 (v2sf a, v2sf b) +NOMIPS16 int test22 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ngl_ps (a, b); } -int test23 (v2sf a, v2sf b) +NOMIPS16 int test23 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ngl_ps (a, b); } -int test24 (v2sf a, v2sf b) +NOMIPS16 int test24 (v2sf a, v2sf b) { return __builtin_mips_upper_c_lt_ps (a, b); } -int test25 (v2sf a, v2sf b) +NOMIPS16 int test25 (v2sf a, v2sf b) { return __builtin_mips_lower_c_lt_ps (a, b); } -int test26 (v2sf a, v2sf b) +NOMIPS16 int test26 (v2sf a, v2sf b) { return __builtin_mips_upper_c_nge_ps (a, b); } -int test27 (v2sf a, v2sf b) +NOMIPS16 int test27 (v2sf a, v2sf b) { return __builtin_mips_lower_c_nge_ps (a, b); } -int test28 (v2sf a, v2sf b) +NOMIPS16 int test28 (v2sf a, v2sf b) { return __builtin_mips_upper_c_le_ps (a, b); } -int test29 (v2sf a, v2sf b) +NOMIPS16 int test29 (v2sf a, v2sf b) { return __builtin_mips_lower_c_le_ps (a, b); } -int test30 (v2sf a, v2sf b) +NOMIPS16 int test30 (v2sf a, v2sf b) { return __builtin_mips_upper_c_ngt_ps (a, b); } -int test31 (v2sf a, v2sf b) +NOMIPS16 int test31 (v2sf a, v2sf b) { return __builtin_mips_lower_c_ngt_ps (a, b); } diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-5.c b/gcc/testsuite/gcc.target/mips/mips-ps-5.c index 23d726e09d07..9e6de0ab81b3 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-5.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-5.c @@ -3,7 +3,7 @@ extern float a[], b[], c[]; -void +NOMIPS16 void foo (void) { int i; diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-6.c b/gcc/testsuite/gcc.target/mips/mips-ps-6.c index 75de478dc8cf..4a6cb60d850d 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-6.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-6.c @@ -9,7 +9,7 @@ typedef float v2sf __attribute__ ((vector_size(8))); -int main () +NOMIPS16 int main () { int little_endian; v2sf a, b, c, d; diff --git a/gcc/testsuite/gcc.target/mips/mips-ps-type.c b/gcc/testsuite/gcc.target/mips/mips-ps-type.c index aca3625ab78a..daa227865c99 100644 --- a/gcc/testsuite/gcc.target/mips/mips-ps-type.c +++ b/gcc/testsuite/gcc.target/mips/mips-ps-type.c @@ -21,79 +21,79 @@ typedef float v2sf __attribute__ ((vector_size(8))); v2sf A = {100, 200}; /* Init from floats */ -v2sf init (float a, float b) +NOMIPS16 v2sf init (float a, float b) { return (v2sf) {a, b}; } /* Move between registers */ -v2sf move (v2sf a) +NOMIPS16 v2sf move (v2sf a) { return a; } /* Load from memory */ -v2sf load () +NOMIPS16 v2sf load () { return A; } /* Store to memory */ -void store (v2sf a) +NOMIPS16 void store (v2sf a) { A = a; } /* Add */ -v2sf add (v2sf a, v2sf b) +NOMIPS16 v2sf add (v2sf a, v2sf b) { return a + b; } /* Subtract */ -v2sf sub (v2sf a, v2sf b) +NOMIPS16 v2sf sub (v2sf a, v2sf b) { return a - b; } /* Negate */ -v2sf neg (v2sf a) +NOMIPS16 v2sf neg (v2sf a) { return - a; } /* Multiply */ -v2sf mul (v2sf a, v2sf b) +NOMIPS16 v2sf mul (v2sf a, v2sf b) { return a * b; } /* Multiply and add */ -v2sf madd (v2sf a, v2sf b, v2sf c) +NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c) { return a * b + c; } /* Multiply and subtract */ -v2sf msub (v2sf a, v2sf b, v2sf c) +NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c) { return a * b - c; } /* Negate Multiply and add */ -v2sf nmadd (v2sf a, v2sf b, v2sf c) +NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c) { return - (a * b + c); } /* Negate Multiply and subtract */ -v2sf nmsub (v2sf a, v2sf b, v2sf c) +NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c) { return - (a * b - c); } /* Conditional Move */ -v2sf cond_move1 (v2sf a, v2sf b, long i) +NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, long i) { if (i > 0) return a; @@ -102,7 +102,7 @@ v2sf cond_move1 (v2sf a, v2sf b, long i) } /* Conditional Move */ -v2sf cond_move2 (v2sf a, v2sf b, int i) +NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i) { if (i > 0) return a; diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 0aaa2a7d9510..00fdb5ec23e7 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -30,7 +30,6 @@ load_lib gcc-dg.exp # # $mips_isa: the ISA level specified by __mips # $mips_arch: the architecture specified by _MIPS_ARCH -# $mips_mips16: true if MIPS16 mode is selected # $mips_gp64: true if 64-bit output is selected # $mips_fp64: true if 64-bit FPRs are selected # $mips_float: "hard" or "soft" @@ -44,7 +43,6 @@ load_lib gcc-dg.exp proc setup_mips_tests {} { global mips_isa global mips_arch - global mips_mips16 global mips_gp64 global mips_fp64 global mips_float @@ -64,9 +62,6 @@ proc setup_mips_tests {} { puts $f { int isa = __mips; const char *arch = _MIPS_ARCH; - #ifdef __mips16 - int mips16 = 1; - #endif #ifdef __mips64 int gp64 = 1; #endif @@ -85,12 +80,11 @@ proc setup_mips_tests {} { regexp {isa = ([^;]*)} $output dummy mips_isa regexp {arch = "([^"]*)} $output dummy mips_arch - set mips_mips16 [regexp {mips16 = 1} $output] set mips_gp64 [regexp {gp64 = 1} $output] set mips_fp64 [regexp {fp64 = 1} $output] regexp {float = "([^"]*)} $output dummy mips_float - set mips_forced_isa [regexp -- {(-mips|-march)} $compiler_flags] + set mips_forced_isa [regexp -- {(-mips[1-5][[:>:]]|-mips32*|-mips64*|-march)} $compiler_flags] set mips_forced_abi [regexp -- {(-mgp|-mfp|-mabi)} $compiler_flags] set mips_forced_float [regexp -- {-m(hard|soft)-float} $compiler_flags] set mips_forced_le [regexp -- {-(EL|mel)[[:>:]]} $compiler_flags] @@ -124,8 +118,8 @@ proc is_gp32_flag {flag} { # # -march=* # -mips* -# Select the target architecture. Skip the test for MIPS16 targets -# or if the multilib flags force a different architecture. +# Select the target architecture. Skip the test if the multilib +# flags force a different architecture. # # -msoft-float # -mhard-float @@ -153,7 +147,6 @@ proc dg-mips-options {args} { global mips_isa global mips_arch - global mips_mips16 global mips_gp64 global mips_fp64 global mips_float @@ -196,11 +189,11 @@ proc dg-mips-options {args} { set matches 0 } } elseif {[regexp -- {^-march=(.*)} $flag dummy arch]} { - if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} { + if {$arch != $mips_arch && $mips_forced_isa} { set matches 0 } } elseif {[regexp -- {^-mips(.*)} $flag dummy isa] && $isa != 16} { - if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} { + if {$isa != $mips_isa && $mips_forced_isa} { set matches 0 } } elseif {[regexp -- {^-m(hard|soft)-float} $flag dummy float]} { diff --git a/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c b/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c index 1aa75770284f..f0f3fda403ec 100644 --- a/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c +++ b/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c @@ -9,22 +9,22 @@ typedef char v4qi __attribute__ ((vector_size(4))); typedef short v2hi __attribute__ ((vector_size(4))); -v2hi add_v2hi (v2hi a, v2hi b) +NOMIPS16 v2hi add_v2hi (v2hi a, v2hi b) { return a + b; } -v4qi add_v4qi (v4qi a, v4qi b) +NOMIPS16 v4qi add_v4qi (v4qi a, v4qi b) { return a + b; } -v2hi sub_v2hi (v2hi a, v2hi b) +NOMIPS16 v2hi sub_v2hi (v2hi a, v2hi b) { return a - b; } -v4qi sub_v4qi (v4qi a, v4qi b) +NOMIPS16 v4qi sub_v4qi (v4qi a, v4qi b) { return a - b; } diff --git a/gcc/testsuite/gcc.target/mips/mips32-dsp.c b/gcc/testsuite/gcc.target/mips/mips32-dsp.c index c65f7b92602e..08f18da6ff20 100644 --- a/gcc/testsuite/gcc.target/mips/mips32-dsp.c +++ b/gcc/testsuite/gcc.target/mips/mips32-dsp.c @@ -103,7 +103,7 @@ typedef int q31; typedef int i32; typedef long long a64; -void test_MIPS_DSP (void); +NOMIPS16 void test_MIPS_DSP (void); char array[100]; int little_endian; @@ -124,27 +124,27 @@ int main () exit (0); } -v2q15 add_v2q15 (v2q15 a, v2q15 b) +NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b) { return __builtin_mips_addq_ph (a, b); } -v4i8 add_v4i8 (v4i8 a, v4i8 b) +NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b) { return __builtin_mips_addu_qb (a, b); } -v2q15 sub_v2q15 (v2q15 a, v2q15 b) +NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b) { return __builtin_mips_subq_ph (a, b); } -v4i8 sub_v4i8 (v4i8 a, v4i8 b) +NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b) { return __builtin_mips_subu_qb (a, b); } -void test_MIPS_DSP () +NOMIPS16 void test_MIPS_DSP () { v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s; v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s; diff --git a/gcc/testsuite/gcc.target/mips/movcc-1.c b/gcc/testsuite/gcc.target/mips/movcc-1.c index 30a0aa7830c8..1f216b7937e9 100644 --- a/gcc/testsuite/gcc.target/mips/movcc-1.c +++ b/gcc/testsuite/gcc.target/mips/movcc-1.c @@ -5,13 +5,13 @@ void ext_int (int); -int +NOMIPS16 int sub1 (int i, int j, int k) { ext_int (k ? i : j); } -int +NOMIPS16 int sub2 (int i, int j, long l) { ext_int (!l ? i : j); diff --git a/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc/testsuite/gcc.target/mips/movcc-2.c index 57c2c507ce7b..bb578099a5b8 100644 --- a/gcc/testsuite/gcc.target/mips/movcc-2.c +++ b/gcc/testsuite/gcc.target/mips/movcc-2.c @@ -5,13 +5,13 @@ void ext_long (long); -long +NOMIPS16 long sub4 (long i, long j, long k) { ext_long (k ? i : j); } -long +NOMIPS16 long sub5 (long i, long j, int k) { ext_long (!k ? i : j); diff --git a/gcc/testsuite/gcc.target/mips/movcc-3.c b/gcc/testsuite/gcc.target/mips/movcc-3.c index ad439f922938..c3e0b422a307 100644 --- a/gcc/testsuite/gcc.target/mips/movcc-3.c +++ b/gcc/testsuite/gcc.target/mips/movcc-3.c @@ -14,49 +14,49 @@ void ext_long (long); void ext_float (float); void ext_double (double); -int +NOMIPS16 int sub3 (int i, int j, float f) { ext_int (f ? i : j); } -long +NOMIPS16 long sub6 (long i, long j, float f) { ext_long (!f ? i : j); } -float +NOMIPS16 float sub7 (float f, float g, int i) { ext_float (i ? f : g); } -float +NOMIPS16 float sub8 (float f, float g, long l) { ext_float (!l ? f : g); } -float +NOMIPS16 float sub9 (float f, float g, float h) { ext_float (h ? f : g); } -double +NOMIPS16 double suba (double f, double g, int i) { ext_double (i ? f : g); } -double +NOMIPS16 double subb (double f, double g, long l) { ext_double (!l ? f : g); } -double +NOMIPS16 double subc (double f, double g, double h) { ext_double (!h ? f : g); diff --git a/gcc/testsuite/gcc.target/mips/msub-1.c b/gcc/testsuite/gcc.target/mips/msub-1.c index d27e6479ef57..ec6bbc5faafd 100644 --- a/gcc/testsuite/gcc.target/mips/msub-1.c +++ b/gcc/testsuite/gcc.target/mips/msub-1.c @@ -2,13 +2,13 @@ /* { dg-mips-options "-O2 -march=vr5400 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmsac\t\\\$0," 2 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return z - (long long) y * x; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/msub-2.c b/gcc/testsuite/gcc.target/mips/msub-2.c index acb7efb2b431..09c22e76632b 100644 --- a/gcc/testsuite/gcc.target/mips/msub-2.c +++ b/gcc/testsuite/gcc.target/mips/msub-2.c @@ -2,13 +2,13 @@ /* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return z - (long long) y * x; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/msub-4.c b/gcc/testsuite/gcc.target/mips/msub-4.c index 8a526f8f5833..df08a6304a4a 100644 --- a/gcc/testsuite/gcc.target/mips/msub-4.c +++ b/gcc/testsuite/gcc.target/mips/msub-4.c @@ -2,13 +2,13 @@ /* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */ /* { dg-final { scan-assembler-times "\tmsub\t\\\$ac" 2 } } */ -long long +NOMIPS16 long long f1 (int x, int y, long long z) { return z - (long long) y * x; } -long long +NOMIPS16 long long f2 (int x, int y, long long z) { long long t = (long long) x * y; diff --git a/gcc/testsuite/gcc.target/mips/msubu-1.c b/gcc/testsuite/gcc.target/mips/msubu-1.c index 9390c473f53f..187cb71c7283 100644 --- a/gcc/testsuite/gcc.target/mips/msubu-1.c +++ b/gcc/testsuite/gcc.target/mips/msubu-1.c @@ -5,13 +5,13 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return z - (ull) y * x; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/msubu-2.c b/gcc/testsuite/gcc.target/mips/msubu-2.c index 75fb404eb975..36cb91bcfa54 100644 --- a/gcc/testsuite/gcc.target/mips/msubu-2.c +++ b/gcc/testsuite/gcc.target/mips/msubu-2.c @@ -5,13 +5,13 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return z - (ull) y * x; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/msubu-4.c b/gcc/testsuite/gcc.target/mips/msubu-4.c index ea4adb1b0805..fb655db87308 100644 --- a/gcc/testsuite/gcc.target/mips/msubu-4.c +++ b/gcc/testsuite/gcc.target/mips/msubu-4.c @@ -5,13 +5,13 @@ typedef unsigned int ui; typedef unsigned long long ull; -ull +NOMIPS16 ull f1 (ui x, ui y, ull z) { return z - (ull) y * x; } -ull +NOMIPS16 ull f2 (ui x, ui y, ull z) { ull t = (ull) x * y; diff --git a/gcc/testsuite/gcc.target/mips/nmadd-1.c b/gcc/testsuite/gcc.target/mips/nmadd-1.c index e027b07d6d7e..bd3b10ab69cb 100644 --- a/gcc/testsuite/gcc.target/mips/nmadd-1.c +++ b/gcc/testsuite/gcc.target/mips/nmadd-1.c @@ -5,25 +5,25 @@ /* { dg-final { scan-assembler "nmsub.s" } } */ /* { dg-final { scan-assembler "nmsub.d" } } */ -float +NOMIPS16 float sub1 (float f, float g, float h) { return -((f * g) + h); } -double +NOMIPS16 double sub2 (double f, double g, double h) { return -((f * g) + h); } -float +NOMIPS16 float sub3 (float f, float g, float h) { return -((f * g) - h); } -double +NOMIPS16 double sub4 (double f, double g, double h) { return -((f * g) - h); diff --git a/gcc/testsuite/gcc.target/mips/nmadd-2.c b/gcc/testsuite/gcc.target/mips/nmadd-2.c index df84a76aad59..cce3710881d7 100644 --- a/gcc/testsuite/gcc.target/mips/nmadd-2.c +++ b/gcc/testsuite/gcc.target/mips/nmadd-2.c @@ -5,25 +5,25 @@ /* { dg-final { scan-assembler "nmsub.s" } } */ /* { dg-final { scan-assembler "nmsub.d" } } */ -float +NOMIPS16 float sub1 (float f, float g, float h) { return -((f * g) + h); } -double +NOMIPS16 double sub2 (double f, double g, double h) { return -((f * g) + h); } -float +NOMIPS16 float sub3 (float f, float g, float h) { return -((f * g) - h); } -double +NOMIPS16 double sub4 (double f, double g, double h) { return -((f * g) - h); diff --git a/gcc/testsuite/gcc.target/mips/rsqrt-1.c b/gcc/testsuite/gcc.target/mips/rsqrt-1.c index 34e712422f4f..885deeff28f6 100644 --- a/gcc/testsuite/gcc.target/mips/rsqrt-1.c +++ b/gcc/testsuite/gcc.target/mips/rsqrt-1.c @@ -6,12 +6,12 @@ extern double sqrt(double); extern float sqrtf(float); -double foo(double x) +NOMIPS16 double foo(double x) { return 1.0/sqrt(x); } -float bar(float x) +NOMIPS16 float bar(float x) { return 1.0f/sqrtf(x); } diff --git a/gcc/testsuite/gcc.target/mips/rsqrt-2.c b/gcc/testsuite/gcc.target/mips/rsqrt-2.c index 4bc3e7f134b5..d3e7aa323a75 100644 --- a/gcc/testsuite/gcc.target/mips/rsqrt-2.c +++ b/gcc/testsuite/gcc.target/mips/rsqrt-2.c @@ -6,12 +6,12 @@ extern double sqrt(double); extern float sqrtf(float); -double foo(double x) +NOMIPS16 double foo(double x) { return sqrt(1.0/x); } -float bar(float x) +NOMIPS16 float bar(float x) { return sqrtf(1.0f/x); } diff --git a/gcc/testsuite/gcc.target/mips/sb1-1.c b/gcc/testsuite/gcc.target/mips/sb1-1.c index c9de3a8dbbb3..cb6b0d83affa 100644 --- a/gcc/testsuite/gcc.target/mips/sb1-1.c +++ b/gcc/testsuite/gcc.target/mips/sb1-1.c @@ -8,22 +8,22 @@ typedef float v2sf __attribute__ ((vector_size (8))); -v2sf divide (v2sf a, v2sf b) +NOMIPS16 v2sf divide (v2sf a, v2sf b) { return a / b; } -v2sf recip (v2sf a) +NOMIPS16 v2sf recip (v2sf a) { return ((v2sf) {1.0, 1.0}) / a; } -v2sf squareroot (v2sf a) +NOMIPS16 v2sf squareroot (v2sf a) { return __builtin_mips_sqrt_ps (a); } -v2sf rsqrt (v2sf a) +NOMIPS16 v2sf rsqrt (v2sf a) { return ((v2sf) {1.0, 1.0}) / __builtin_mips_sqrt_ps (a); } diff --git a/gcc/testsuite/gcc.target/mips/vr-mult-1.c b/gcc/testsuite/gcc.target/mips/vr-mult-1.c index 47d639131b9f..9ea55af44a52 100644 --- a/gcc/testsuite/gcc.target/mips/vr-mult-1.c +++ b/gcc/testsuite/gcc.target/mips/vr-mult-1.c @@ -2,6 +2,6 @@ is preferred over mtlo/msac. */ /* { dg-do compile } */ /* { dg-mips-options "-O2 -march=vr5400" } */ -int f1 (int a, int b, int c) { return a + b * c; } -int f2 (int a, int b, int c) { return a - b * c; } +NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; } +NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; } /* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/vr-mult-2.c b/gcc/testsuite/gcc.target/mips/vr-mult-2.c index 9112ed08c829..0ff3d47de701 100644 --- a/gcc/testsuite/gcc.target/mips/vr-mult-2.c +++ b/gcc/testsuite/gcc.target/mips/vr-mult-2.c @@ -2,6 +2,6 @@ is preferred over mtlo/msac. */ /* { dg-do compile } */ /* { dg-mips-options "-O2 -march=vr5500" } */ -int f1 (int a, int b, int c) { return a + b * c; } -int f2 (int a, int b, int c) { return a - b * c; } +NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; } +NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; } /* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */ diff --git a/gcc/testsuite/lib/fortran-torture.exp b/gcc/testsuite/lib/fortran-torture.exp index d97c2cefc616..92a46e1c9179 100644 --- a/gcc/testsuite/lib/fortran-torture.exp +++ b/gcc/testsuite/lib/fortran-torture.exp @@ -42,7 +42,8 @@ if ![info exists TORTURE_OPTIONS] { lappend vectorizer_options "-msse2" set test_tree_vectorize 1 } elseif { [istarget "mipsisa64*-*-*"] - && [check_effective_target_mpaired_single] } { + && [check_effective_target_mpaired_single] + && [check_effective_target_nomips16] } { lappend vectorizer_options "-mpaired-single" set test_tree_vectorize 1 } elseif [istarget "sparc*-*-*"] { diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index c7c0ceeab74f..07a1dc9f1eeb 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -625,6 +625,21 @@ proc check_effective_target_mips64 { } { }] } +# Return true if the target is a MIPS target that does not produce +# MIPS16 code. + +proc check_effective_target_nomips16 { } { + return [check_no_compiler_messages nomips16 object { + #ifndef __mips + #error FOO + #else + /* A cheap way of testing for -mflip-mips16. */ + void foo (void) { asm ("addiu $20,$20,1"); } + void bar (void) { asm ("addiu $20,$20,1"); } + #endif + }] +} + # Add the options needed for MIPS16 function attributes. At the moment, # we don't support MIPS16 PIC.