From: Chen Wang <unicorn_wang@outlook.com>
Date: Wed, 5 Feb 2025 07:01:34 +0000 (+0800)
Subject: riscv: sophgo: dts: add pwm controller for SG2042 SoC
X-Git-Tag: v6.15-rc1~159^2~7^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=255f83ba5c16b0f79ad0c46c69b2e907012bde83;p=thirdparty%2Fkernel%2Flinux.git

riscv: sophgo: dts: add pwm controller for SG2042 SoC

SG2042 has one PWM controller, which has 4 pwm output channels.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/f376e16c0ee0cdac51bb91421d78defc0601627a.1738737617.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index e62ac51ac55ab..4449c762d6631 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -165,6 +165,15 @@
 			};
 		};
 
+		pwm: pwm@703000c000 {
+			compatible = "sophgo,sg2042-pwm";
+			reg = <0x70 0x3000c000 0x0 0x20>;
+			#pwm-cells = <3>;
+			clocks = <&clkgen GATE_CLK_APB_PWM>;
+			clock-names = "apb";
+			resets = <&rstgen RST_PWM>;
+		};
+
 		pllclk: clock-controller@70300100c0 {
 			compatible = "sophgo,sg2042-pll";
 			reg = <0x70 0x300100c0 0x0 0x40>;