From: Greg Kroah-Hartman Date: Sat, 12 Jul 2025 12:09:00 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v5.15.188~83 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=256621ee5bfdf97effcb2b9d70fa09a1a7c417d4;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: x86-cpu-amd-properly-check-the-tsa-microcode.patch --- diff --git a/queue-5.4/series b/queue-5.4/series index eb09099cb4..a1aa504363 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -119,3 +119,4 @@ atm-clip-fix-memory-leak-of-struct-clip_vcc.patch atm-clip-fix-infinite-recursive-call-of-clip_push.patch atm-clip-fix-null-pointer-dereference-in-vcc_sendmsg.patch net-sched-abort-__tc_modify_qdisc-if-parent-class-do.patch +x86-cpu-amd-properly-check-the-tsa-microcode.patch diff --git a/queue-5.4/x86-cpu-amd-properly-check-the-tsa-microcode.patch b/queue-5.4/x86-cpu-amd-properly-check-the-tsa-microcode.patch new file mode 100644 index 0000000000..1cfc01a99c --- /dev/null +++ b/queue-5.4/x86-cpu-amd-properly-check-the-tsa-microcode.patch @@ -0,0 +1,56 @@ +From bp@alien8.de Sat Jul 12 14:01:48 2025 +From: Borislav Petkov +Date: Fri, 11 Jul 2025 21:18:44 +0200 +Subject: x86/CPU/AMD: Properly check the TSA microcode +To: stable@vger.kernel.org +Cc: Thomas Voegtle , kim.phillips@amd.com +Message-ID: <20250711191844.GIaHFjlJiQi_HxyyWG@fat_crate.local> +Content-Disposition: inline + +From: "Borislav Petkov (AMD)" + +In order to simplify backports, I resorted to an older version of the +microcode revision checking which didn't pull in the whole struct +x86_cpu_id matching machinery. + +My simpler method, however, forgot to add the extended CPU model to the +patch revision, which lead to mismatches when determining whether TSA +mitigation support is present. + +So add that forgotten extended model. + +This is a stable-only fix and the preference is to do it this way +because it is a lot simpler. Also, the Fixes: tag below points to the +respective stable patch. + +Fixes: 7a0395f6607a ("x86/bugs: Add a Transient Scheduler Attacks mitigation") +Reported-by: Thomas Voegtle +Signed-off-by: Borislav Petkov (AMD) +Tested-by: Thomas Voegtle +Message-ID: <04ea0a8e-edb0-c59e-ce21-5f3d5d167af3@lio96.de> +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/amd.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c +index 8a740e92e483..b42307200e98 100644 +--- a/arch/x86/kernel/cpu/amd.c ++++ b/arch/x86/kernel/cpu/amd.c +@@ -376,6 +376,7 @@ static bool amd_check_tsa_microcode(void) + + p.ext_fam = c->x86 - 0xf; + p.model = c->x86_model; ++ p.ext_model = c->x86_model >> 4; + p.stepping = c->x86_stepping; + + if (cpu_has(c, X86_FEATURE_ZEN3) || +-- +2.43.0 + +-- +Regards/Gruss, + Boris. + +https://people.kernel.org/tglx/notes-about-netiquette +